How to compile it to verilog!

[myjtag]

Hi,
I have installed sbt on my windows machine, and when I run make it would generate these errors,

git submodule update --init berkeley-testfloat-3
fatal: not a git repository (or any of the parent directories): .git
make: *** [Makefile:9: berkeley-testfloat-3/.git] Error 128

So How should I Generate Verilog for implementation of FPGA?

[HaFred]

ChiselTester should have the Verilog dumping function as long as you get through the sbt process.