I’m porting a Gemmini + Rocket design to Digilent Arty Z7-20 (Zynq-7020, xc7z020-1clg400C).
During implementation on Vivado I hit LUT as Distributed RAM over-utilized DRC errors. I’d like advice on reducing LUT usage (prefer BRAM mapping) and whether moving to a 32-bit ISA (RV32) + small Rocket core is the right approach for this board?
I’m porting a Gemmini + Rocket design to Digilent Arty Z7-20 (Zynq-7020, xc7z020-1clg400C).
During implementation on Vivado I hit LUT as Distributed RAM over-utilized DRC errors. I’d like advice on reducing LUT usage (prefer BRAM mapping) and whether moving to a 32-bit ISA (RV32) + small Rocket core is the right approach for this board?