MachineV

Simple CPU implementation in Verilog

Micro-programmed CPU with customizable instruction set
JSON instruction definitions compiled into raw signal memory bitstream
Simple assembler that works well with custom instructions
Simple character-based GPU with VGA output (target device clock must be divisible by 25MHz)

Project is still in its development stage

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
.gitignore		.gitignore
ALU.v		ALU.v
ALU_tb.v		ALU_tb.v
ControlUnit.v		ControlUnit.v
Divider.v		Divider.v
Divider_tb.v		Divider_tb.v
IRegister.v		IRegister.v
LCounter.v		LCounter.v
LCounter_tb.v		LCounter_tb.v
MachineV.v		MachineV.v
MachineV_tb.v		MachineV_tb.v
MachineV_tb.wcfg		MachineV_tb.wcfg
Memory.v		Memory.v
Memory_tb.v		Memory_tb.v
README.md		README.md
SPRegister.v		SPRegister.v
VGA.v		VGA.v
VGAClock.v		VGAClock.v
assembler.js		assembler.js
bcd2seg.v		bcd2seg.v
font.py		font.py
initial_program.asm		initial_program.asm
instructions.js		instructions.js
instructions.json		instructions.json
lengths.mem		lengths.mem
pre_synthesis.bat		pre_synthesis.bat
top.v		top.v
vga_font.png		vga_font.png