RAH Protocol User Guide

Overview

The RAH (Real-time Application Handler) protocol is designed to facilitate the transfer of data between a CPU and an FPGA, developed by Vicharak. It enables the CPU to run various applications that send data to the FPGA. The RAH Services encapsulate the data into distinguishable data-frames identified by an app_id and deliver these frames to the FPGA. On the FPGA side, the RAH design decodes the data and writes it to the corresponding APP_WR_FIFO. Similarly, during the read cycle, the FPGA writes data into APP_RD_FIFO, which is then encapsulated and delivered back to the CPU where it gets decoded.

This section describes the key components and the data transfer process between the CPU and FPGA.

Block Diagram

Key Components

1. CPU Applications: These applications generate data that needs to be sent to the FPGA.
2. RAH Services: Encapsulates and decapsulates data frames based on the app_id.
3. FPGA RAH Design: Handles the decoding of incoming data frames and writes to the appropriate FIFO.
4. APP_WR_FIFO: FIFO buffer where decoded data from CPU is written.
5. APP_RD_FIFO: FIFO buffer where data generated by FPGA applications is written before being sent to the CPU.

Data Transfer Process

Write Cycle (CPU to FPGA)

1. CPU Application: Generates data to be sent to the FPGA.
2. RAH Services on CPU: Encapsulates the data into a data-frame, including the app_id.
3. RAH Design on FPGA: Receives the data-frame and decodes it.
4. FPGA Application: Reads the decoded data from the appropriate APP_WR_FIFO.

Read Cycle (FPGA to CPU)

1. FPGA Application: Writes data to the APP_RD_FIFO.
2. RAH Design on FPGA: Encapsulates the data from APP_RD_FIFO into a data-frame.
3. RAH Services on CPU: Receives the data-frame and decodes it.
4. CPU Application: Processes the received data.

Data Alignment

Note

The alignment of data to be sent and received throughout the RAH protocol is user-defined. The user must ensure that the data is sampled in the same way as it is aligned at the time of transmission. This applies to both write and read cycles.

Generating Multiple Applications

Pre-requisite

1. Enable FPGA Communication from the Vicharak Utility

   • Enabling the overlay

2. Install RAH Service on the Board:

   sudo apt update
   sudo apt install rah-service

Note

RAH service is frequently updated, so it is recommended to update the RAH service before using it on both:w CPU side as well as FPGA side.

RAH Protocol User Guide - Resources

For further details on how to use the RAH protocol, you can refer to the following guides:

1. CPU Usage Guide:
   This guide will provide detailed instructions on how to set up and use the RAH protocol on the CPU side, including configuration, data encapsulation, and integration with CPU applications.

2. FPGA Implementation Guide:
   This guide covers the FPGA side of the RAH protocol, explaining how to implement the RAH design, decode data frames, and manage the FIFO buffers for both write and read cycles.

3. RAH Example Integration:
   This document provides a step-by-step example of integrating the RAH protocol between the CPU and FPGA, demonstrating the complete flow from data generation on the CPU to processing on the FPGA and back.