Fix software PLL not locked in FFVA-INT (AEC not converge in FFVA-INT) #393
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xross
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Aug 28, 2025
examples/ffva/src/main.c
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| uint16_t mclk_pt = port_get_trigger_time(i2s_callback_args->p_mclk_count); // Immediately sample mclk_count | ||
| uint16_t bclk_pt = port_get_trigger_time(i2s_callback_args->p_bclk_count); // Now grab bclk_count (which won't have changed) | ||
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Please dont add white space :) (Best to config your editor to remove if you can)
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Hi Ross
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In FFVA-INT example, software PLL is used to phase lock MCLK with BCLK to eliminate the need of external MCLK.
However, sw_pll_lut_do_control in the original code is called every 240 I2S frame instead of every I2S frame.
This causes the software PLL failed to lock, thus the AEC not converge in FFVA-INT.
This PR put the sw_pll_lut_do_control call in I2S restart callback; this make sure it is called in every I2S frame.
This PR rely on the PR#256 on fwk_rtos, PR#256 need to be merged before this PR can compile.