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104 changes: 104 additions & 0 deletions .github/workflows/pr.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,104 @@
name: Pull Request Check

on:
pull_request:
branches: ['main']

env:
SCALA_VERSION: '2.12'
PROJECT_NAME: 'spinalutils'

jobs:
build-and-package:
runs-on: ubuntu-latest
steps:
- name: Checkout repository
uses: actions/checkout/@v4

- name: Setup Java
uses: actions/setup-java@v3
with:
distribution: 'temurin'
java-version: '17'

- name: Install sbt
run: |
# Install sbt
SBT_VERSION=1.9.7
curl -fLO "https://github.com/sbt/sbt/releases/download/v$SBT_VERSION/sbt-$SBT_VERSION.tgz"
sudo tar -xzf "sbt-$SBT_VERSION.tgz" -C /usr/share
sudo ln -s /usr/share/sbt/bin/sbt /usr/bin/sbt

# Verify Installation
sbt sbtVersion

- name: Extract Project Version
id: get_version
run: |
# get project version
VERSION=$(awk -F'"' '/ThisBuild \/ version :=/ {print $2}' build.sbt)
if [ -z "$VERSION" ]; then
echo "::error::Failed to extract version from build.sbt"
echo "Looking for pattern: ThisBuild / version := \"...\""
exit 1
fi

echo "Extracted version from build.sbt: $VERSION"
echo "version=$VERSION" >> $GITHUB_OUTPUT

- name: Import GPG Key
id: import_gpg
env:
GPG_PRIVATE_KEY: ${{ secrets.GPG_PRIVATE_KEY }}
GPG_PASSPHRASE: ${{ secrets.GPG_PRIVATE_KEY_PASSWORD }}
run: |
echo "$GPG_PRIVATE_KEY" | gpg --batch --import

echo "use-agent" >> ~/.gnupg/gpg.conf
echo "allow-loopback-pinentry" >> ~/.gnupg/gpg-agent.conf
echo "default-cache-ttl 86400" >> ~/.gnupg/gpg-agent.conf
echo "max-cache-ttl 604800" >> ~/.gnupg/gpg-agent.conf
gpgconf --kill gpg-agent
gpgconf --reload gpg-agent

echo "$GPG_PASSPHRASE" | gpg --batch --pinentry-mode loopback --passphrase-fd 0 --sign ~/.gnupg/gpg-agent.conf
rm ~/.gnupg/gpg-agent.conf.gpg

- name: Build project
run: |
sbt clean compile package packageSrc packageDoc makePom

- name: Package and Sign artifacts
id: package_and_sign
env:
PROJECT_VERSION: ${{ steps.get_version.outputs.version }}
run: |
TARGET_DIR="target/scala-$SCALA_VERSION"
cd $TARGET_DIR

for file in *.jar *.pom; do
echo "${{ secrets.GPG_PRIVATE_KEY_PASSWORD }}" | gpg --batch --pinentry-mode loopback --passphrase-fd 0 --detach-sign --armor "$file"

md5sum "$file" | awk '{print $1}' > "${file}.md5"
sha1sum "$file" | awk '{print $1}' > "${file}.sha1"
done

ZIP_NAME="${PROJECT_NAME}_${SCALA_VERSION}-${PROJECT_VERSION}-dist.zip"
ZIP_PREFIX="${PROJECT_NAME}_${SCALA_VERSION}-${PROJECT_VERSION}"
TAR_PATH="io/github/xueweiwujxw/${PROJECT_NAME}_${SCALA_VERSION}/${PROJECT_VERSION}"
mkdir -p $TAR_PATH
cp $ZIP_PREFIX* $TAR_PATH
zip -r $ZIP_NAME $TAR_PATH

cd ../../

echo "artifact_path=$TARGET_DIR/$ZIP_NAME" >> $GITHUB_OUTPUT
echo "publish_dir=$TARGET_DIR" >> $GITHUB_OUTPUT

- name: Upload Artifacts
uses: actions/upload-artifact@v4
with:
name: release-bundle
path: |
target/scala-${{ env.SCALA_VERSION }}/${{ env.PROJECT_NAME }}_${{ env.SCALA_VERSION }}-${{ steps.get_version.outputs.version }}-dist.zip
retention-days: 1
1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
*.class
*.log
*.bak
*.txt

# sbt specific
.cache/
Expand Down
2 changes: 2 additions & 0 deletions README.md
Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
## Utils Based on SpinalHDL

[![Maven Central Version](https://img.shields.io/maven-central/v/io.github.xueweiwujxw/spinalutils_2.12.svg?label=Maven%20Central&logo=scala)](https://central.sonatype.com/artifact/io.github.xueweiwujxw/spinalutils_2.12)

This repository uses SpinalHDL to implement some FPGA algorithms, building scripts for some Xilinx IP cores and primitive descriptions which can be easily used througn `BlackBox`.

### Reference
Expand Down
19 changes: 17 additions & 2 deletions build.sbt
Original file line number Diff line number Diff line change
@@ -1,14 +1,29 @@
ThisBuild / version := "0.1.4"
ThisBuild / scalaVersion := "2.12.18"
ThisBuild / organization := "com.github.xueweiwujxw"
ThisBuild / organization := "io.github.xueweiwujxw"

val spinalVersion = "1.11.0"
publishMavenStyle := true

val spinalVersion = "1.12.2"
val spinalCore = "com.github.spinalhdl" %% "spinalhdl-core" % spinalVersion
val spinalLib = "com.github.spinalhdl" %% "spinalhdl-lib" % spinalVersion
val spinalIdslPlugin = compilerPlugin(
"com.github.spinalhdl" %% "spinalhdl-idsl-plugin" % spinalVersion
)

description := "Utils collection based on SpinalHDL"
homepage := Some(url("https://github.com/xueweiwujxw/SpinalUtils"))
scmInfo := Some(
ScmInfo(
url("https://github.com/xueweiwujxw/SpinalUtils"),
"scm:git@github.com:xueweiwujxw/SpinalUtils.git"
)
)
developers := List(
Developer(id = "xueweiwujxw", name = "Wlanxww", email = "xueweiwujxw@outlook.com", url = url("https://wlanxww.com"))
)
licenses := Seq("BSD 3-Clause" -> new URL("https://opensource.org/licenses/BSD-3-Clause"))

lazy val spinalUtils = (project in file("."))
.settings(
name := "spinalUtils",
Expand Down
172 changes: 0 additions & 172 deletions src/main/scala/spinalutils/libs/axispi/Axi4SpiMaster.scala
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
package spinalutils.libs.axispi


import spinal.core._
import spinal.lib._
import spinal.lib.bus.amba4.axi._
Expand Down Expand Up @@ -42,174 +41,3 @@ case class Axi4SpiMaster(config: Axi4SpiMasterConfig) extends Component {
noIoPrefix()
Axi4SpecRenamer(io.s_axi)
}

object Axi4SpiMasterGen extends App {
SpinalVerilog(
Axi4SpiMaster(
config = Axi4SpiMasterConfig(
axiConfig = Axi4Config(
addressWidth = 12,
dataWidth = 32,
useBurst = true,
idWidth = 4,
useRegion = false,
useProt = true,
useCache = true,
useLock = true,
useQos = false
),
spiConfig = SpiMasterCtrlGenerics(
ssWidth = 8,
timerWidth = 4,
dataWidth = 8
)
)
)
)
}

import spinal.sim._
import spinal.core.sim._
import spinal.lib.bus.amba4.axi.sim._

object Axi4SpiMasterSim extends App {
SimConfig.withFstWave.doSim(
Axi4SpiMaster(
config = Axi4SpiMasterConfig(
axiConfig = Axi4Config(
addressWidth = 12,
dataWidth = 32,
useBurst = true,
idWidth = 4,
useRegion = false,
useProt = true,
useCache = true,
useLock = true,
useQos = false
),
spiConfig = SpiMasterCtrlGenerics(
ssWidth = 8,
timerWidth = 4,
dataWidth = 8
)
)
)
) { dut =>
dut.io.m_spi.miso #= false
dut.io.s_axi.ar.valid #= false
dut.io.s_axi.aw.valid #= false
dut.io.s_axi.w.valid #= false

dut.clockDomain.forkStimulus(20 MHz)
val axiMaster = Axi4Master(dut.io.s_axi, dut.clockDomain, "Axi4SpiMaster")

var threadRunning = true
val ssAllTrue = (BigInt(1) << dut.config.spiConfig.ssWidth) - 1

def hasSS = dut.io.m_spi.ss.toBigInt != ssAllTrue

val misoThread = fork {
while (threadRunning) {
dut.clockDomain.waitSamplingWhere(hasSS || !threadRunning)
var i = 0
while (threadRunning && hasSS) {
dut.io.m_spi.miso #= i % 2 == 1
if (hasSS) {
dut.clockDomain.waitRisingEdgeWhere(dut.io.m_spi.sclk.toBoolean || !hasSS)
if (hasSS)
i += 1
}
}
}
}

dut.clockDomain.waitSampling(10)

println("disable cmd en")
axiMaster.write(0x1c, List(0x00.toByte, 0, 0, 0))

println("set cpha as 0 and cpol as 0")
axiMaster.write(8, List(0), burst = Axi4Bursts.Fixed)
println("set sclkToggle as 0")
axiMaster.write(0xc, List(0), burst = Axi4Bursts.Fixed)
println("set ssSetup as 0")
axiMaster.write(0x10, List(0), burst = Axi4Bursts.Fixed)
println("set ssHold as 0")
axiMaster.write(0x14, List(0), burst = Axi4Bursts.Fixed)
println("set ssDisable as 0")
axiMaster.write(0x18, List(4), burst = Axi4Bursts.Fixed)
println("enable cmd intr amd rsp intr")
axiMaster.write(0x4, List(0x03), burst = Axi4Bursts.Fixed)

println("first spi transfer")

println("enable chip 1")
axiMaster.write(0, List(0x01.toByte, 0, 0, 0x11.toByte))

println("write 0xa5 to spi")
axiMaster.write(0, List(0xa5.toByte, 0, 0, 0x00.toByte))

println("write 0x96 to spi and read from spi")
axiMaster.write(0, List(0x96.toByte, 0, 0, 0x01.toByte))

println("write 0x00 to spi and read from spi")
axiMaster.write(0, List(0x00.toByte, 0, 0, 0x01.toByte))

println("disable chip 0")
axiMaster.write(0, List(0x01.toByte, 0, 0, 0x10.toByte))

println("enable cmd en")
axiMaster.write(0x1c, List(0x01.toByte))
dut.clockDomain.waitSamplingWhere(dut.io.m_spi.ss.toBigInt == 0xff)
println("disable cmd en")
axiMaster.write(0x1c, List(0x00.toByte))

println("read status")
axiMaster.read(4, 4)

println("read data")
axiMaster.read(0, 1)
println("read data")
axiMaster.read(0, 1)

dut.clockDomain.waitSampling(50)

println("second spi transfer")

println("enable chip 1")
axiMaster.write(0, List(0x01.toByte, 0, 0, 0x11.toByte))

println("write 0xa5 to spi")
axiMaster.write(0, List(0xa5.toByte, 0, 0, 0x00.toByte))

println("write 0x96 to spi and read from spi")
axiMaster.write(0, List(0x96.toByte, 0, 0, 0x01.toByte))

println("write 0x00 to spi and read from spi")
axiMaster.write(0, List(0x00.toByte, 0, 0, 0x01.toByte))

println("disable chip 0")
axiMaster.write(0, List(0x01.toByte, 0, 0, 0x10.toByte))

println("enable cmd en")
axiMaster.write(0x1c, List(0x01.toByte))
dut.clockDomain.waitSamplingWhere(dut.io.m_spi.ss.toBigInt == 0xff)
println("disable cmd en")
axiMaster.write(0x1c, List(0x00.toByte))

println("read status")
axiMaster.read(4, 4)

println("read data")
axiMaster.read(0, 1)
println("read data")
axiMaster.read(0, 1)

axiMaster.read(0x20, 4)

dut.clockDomain.waitSampling(50)

threadRunning = false
misoThread.join()
}
}
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