The project aims at performing high-level synthesis on an input expression written in a high-level format to generate the hardware level code in the VHDL and some graphical representations for easier viewing. It goes through the processes of Scheduling, Binding and Allocation on a tree produced from the input infix expression while optimizing, based on the constraints on the timing and resources to generate an internal representation. This is then worked upon further to generate a synthesizable VHDL component which can be used by the user to perform the operation as desired.
Right now the project is in initial stage and we are open for new ideas and would be very pleased by your contribution.