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stm32H7 external NOR ospi flash in memorymapped mode #62349

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stm32H7 external NOR ospi flash in memorymapped mode #62349

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4830c7c
drivers: flash: stm32 flash base address from the DTS node
FRASTM Jan 23, 2024
3291b4c
drivers: flash: stm32 flash driver has a Kconfig STM32_MEMMAP
FRASTM Aug 2, 2023
44a1934
drivers: flash: stm32 ospi drivers with Memorymapped mode
FRASTM Jun 1, 2023
aeed3d3
drivers: flash: stm32 ospi driver aborts memmap before erase/write
FRASTM Jan 24, 2024
5e10f8a
soc: arm: stm32u5 device with DCACHE for writing to NOR flash
FRASTM Sep 6, 2023
84aca6d
boards: arm: stm32u585 disco kit for XiP on external octoflash
FRASTM Aug 31, 2023
2d582f4
samples: subsys: fs_little fs on stm32u585 disco in xip
FRASTM Jan 23, 2024
8b6b9ab
drivers: clock control of the stm32h7 skips pll1 re-init
FRASTM Sep 15, 2023
1b1e047
dts: arm: stm32h7 MPU attribute for the external Memory
FRASTM Jan 26, 2024
d9a03a8
boards: arm: stm32h7b3 disco kit for XiP on external octoflash
FRASTM Sep 4, 2023
c54eca3
samples: subsys: fs_little fs on stm32h7b3 disco in xip
FRASTM Jan 23, 2024
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11 changes: 6 additions & 5 deletions boards/arm/b_u585i_iot02a/b_u585i_iot02a-common.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -131,11 +131,10 @@ stm32_lp_tick_source: &lptim1 {

status = "okay";

mx25lm51245: ospi-nor-flash@0 {
mx25lm51245: ospi-nor-flash@70000000 {
compatible = "st,stm32-ospi-nor";
reg = <0>;
reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits */
ospi-max-frequency = <DT_FREQ_M(50)>;
size = <DT_SIZE_M(512)>; /* 64 MBytes */
Comment on lines +134 to -138
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If this is also valid in non memmap cases, let's make it a dedicated PR, extended to all similar descriptions in STM32 boards

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During the MemoryMapped mode, the driver controls the external flash base address and size.
Both values are given by this property (better solution than using a definition in the board Kconfig).
The property exists. Here it is filled with actual values of the external flash when the external flash is accessed in memorymapped mode.
When the external flash is accessed in indirect mode (non-MemoryMapped), the base address is useless and the size is given by the property.

spi-bus-width = <OSPI_OPI_MODE>;
data-rate = <OSPI_DTR_TRANSFER>;
four-byte-opcodes;
Expand All @@ -146,8 +145,10 @@ stm32_lp_tick_source: &lptim1 {
#address-cells = <1>;
#size-cells = <1>;

partition@0 {
reg = <0x00000000 DT_SIZE_M(64)>;
/* put image at the offset of slot1 */
slot1_partition:partition@100000 {
label = "image-1";
reg = <0x00100000 DT_SIZE_K(416)>;
};
};
};
Expand Down
6 changes: 1 addition & 5 deletions boards/arm/b_u585i_iot02a/b_u585i_iot02a.dts
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Expand Up @@ -16,7 +16,6 @@
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};

aliases {
Expand Down Expand Up @@ -45,10 +44,7 @@
label = "image-0";
reg = <0x00010000 DT_SIZE_K(416)>;
};
slot1_partition: partition@78000 {
label = "image-1";
reg = <0x00078000 DT_SIZE_K(416)>;
};

scratch_partition: partition@e0000 {
label = "image-scratch";
reg = <0x000e0000 DT_SIZE_K(64)>;
Expand Down
41 changes: 35 additions & 6 deletions boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.dts
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Expand Up @@ -242,6 +242,35 @@
def-back-color-blue = <0xFF>;
};

&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
read-only;
};

/*
* The flash starting at offset 0x10000 and ending at
* offset 0x1ffff is reserved for use by the application.
*/

slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_K(800)>;
};

scratch_partition: partition@f8000 {
label = "image-scratch";
reg = <0x000F8000 DT_SIZE_K(16)>;
};
};
};

&octospi1 {
pinctrl-0 = <&octospim_p1_clk_pb2 &octospim_p1_ncs_pg6
&octospim_p1_io0_pd11 &octospim_p1_io1_pf9
Expand All @@ -253,11 +282,10 @@

status = "okay";

mx25lm51245: ospi-nor-flash@0 {
mx25lm51245: ospi-nor-flash@90000000 {
compatible = "st,stm32-ospi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Megabits */
ospi-max-frequency = <DT_FREQ_M(50)>;
size = <DT_SIZE_M(512)>; /* 512 Megabits */
spi-bus-width = <OSPI_OPI_MODE>;
data-rate = <OSPI_DTR_TRANSFER>;
status = "okay";
Expand All @@ -267,9 +295,10 @@
#address-cells = <1>;
#size-cells = <1>;

partition@0 {
label = "nor";
reg = <0x00000000 DT_SIZE_M(4)>;
/* put image at offset 0 in slot1 */
slot1_partition:partition@0 {
label = "image-1";
reg = <0x00000000 DT_SIZE_K(800)>;
};
};
};
Expand Down
7 changes: 7 additions & 0 deletions boards/arm/stm32h7b3i_dk/support/openocd.cfg
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Expand Up @@ -20,3 +20,10 @@ set CORE_RESET 0

source [find target/stm32h7x.cfg]

# Due to the use of connect_assert_srst, running gdb requires
# to reset halt just after openocd init.
rename init old_init
proc init {} {
old_init
reset halt
}
6 changes: 6 additions & 0 deletions drivers/clock_control/clock_stm32_ll_h7.c
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Expand Up @@ -666,6 +666,12 @@ __unused
static int set_up_plls(void)
{
#if defined(STM32_PLL_ENABLED) || defined(STM32_PLL2_ENABLED) || defined(STM32_PLL3_ENABLED)

/* Skip if PLL1 is already configured */
if (LL_RCC_PLL1_IsReady()) {
return 0;
}

int r;
uint32_t vco_input_range;
uint32_t vco_output_range;
Expand Down
7 changes: 7 additions & 0 deletions drivers/flash/Kconfig.stm32
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Expand Up @@ -72,4 +72,11 @@ config FLASH_STM32_BLOCK_REGISTERS
registers improves system security, because flash content (or
protection settings) can't be changed even when exploit was found.

config STM32_MEMMAP
bool "NOR Flash in MemoryMapped for XiP"
depends on XIP
help
This option enables the XIP mode for the external NOR flash
mounted on STM32 boards.

endif # SOC_FLASH_STM32
7 changes: 4 additions & 3 deletions drivers/flash/flash_stm32.c
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Expand Up @@ -157,7 +157,7 @@ static void flash_stm32_flush_caches(const struct device *dev,
regs->ACR |= FLASH_ACR_DCEN;
}
#elif defined(CONFIG_SOC_SERIES_STM32F7X)
SCB_InvalidateDCache_by_Addr((uint32_t *)(CONFIG_FLASH_BASE_ADDRESS
SCB_InvalidateDCache_by_Addr((uint32_t *)(FLASH_STM32_BASE_ADDRESS
+ offset), len);
#endif
}
Expand All @@ -178,7 +178,7 @@ static int flash_stm32_read(const struct device *dev, off_t offset,

LOG_DBG("Read offset: %ld, len: %zu", (long int) offset, len);

memcpy(data, (uint8_t *) CONFIG_FLASH_BASE_ADDRESS + offset, len);
memcpy(data, (uint8_t *) FLASH_STM32_BASE_ADDRESS + offset, len);

return 0;
}
Expand Down Expand Up @@ -562,7 +562,8 @@ static int stm32_flash_init(const struct device *dev)

flash_stm32_sem_init(dev);

LOG_DBG("Flash initialized. BS: %zu",
LOG_DBG("Flash @0x%x initialized. BS: %zu",
FLASH_STM32_BASE_ADDRESS,
flash_stm32_parameters.write_block_size);

/* Check Flash configuration */
Expand Down
3 changes: 3 additions & 0 deletions drivers/flash/flash_stm32.h
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Expand Up @@ -17,6 +17,9 @@
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#endif

/* Get the base address of the flash from the DTS node */
#define FLASH_STM32_BASE_ADDRESS DT_REG_ADDR(DT_INST(0, st_stm32_nv_flash))

struct flash_stm32_priv {
FLASH_TypeDef *regs;
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \
Expand Down
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