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stm32 XiP with ospi external NOR flash #64641

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@FRASTM FRASTM commented Oct 31, 2023

Gives example to execute an application from the external octo NOR flash in XiP mode

  1. build and link an application for the external NOR with sysbuild
  2. define the external NOR flash base address
  3. flash the mcuboot binary file at 0x8000000 and the zephyr.signed bianry file at this external NOR flash base address

Requires patching the ../bootloader/mcuboot/boot/flash_map_extended.c:

diff --git a/boot/zephyr/flash_map_extended.c b/boot/zephyr/flash_map_extended.c
index 64e80085..01cd7465 100644
--- a/boot/zephyr/flash_map_extended.c
+++ b/boot/zephyr/flash_map_extended.c
@@ -18,7 +18,19 @@
 
 BOOT_LOG_MODULE_DECLARE(mcuboot);
 
-#if (!defined(CONFIG_XTENSA) && DT_HAS_CHOSEN(zephyr_flash_controller))
+#if defined(CONFIG_STM32_MEMMAP)
+/* MEMORY MAPPED for XiP on external NOR flash takes the ospi-nor or qspi-nor device */
+#define FLASH_DEVICE_ID SPI_FLASH_0_ID
+#if DT_NODE_HAS_STATUS(DT_INST(0, st_stm32_ospi_nor), okay)
+#define FLASH_DEVICE_NODE DT_INST(0, st_stm32_ospi_nor)
+#elif DT_NODE_HAS_STATUS(DT_INST(0, st_stm32_qspi_nor), okay)
+#define FLASH_DEVICE_NODE DT_INST(0, st_stm32_qspi_nor)
+#else
+#error "FLASH_DEVICE_NODE could not be determined"
+#endif
+#define FLASH_DEVICE_BASE CONFIG_STM32_MEMMAP_EXT_FLASH_BASE_ADDRESS
+
+#elif (!defined(CONFIG_XTENSA) && DT_HAS_CHOSEN(zephyr_flash_controller))
 #define FLASH_DEVICE_ID SOC_FLASH_0_ID
 #define FLASH_DEVICE_BASE CONFIG_FLASH_BASE_ADDRESS
 #define FLASH_DEVICE_NODE DT_CHOSEN(zephyr_flash_controller)

Requires a ../bootloader/mcuboot/boot/zephyr/boards/ .conf and .overlay files to set
CONFIG_BOOT_DIRECT_XIP=y
CONFIG_STM32_MEMMAP=y
CONFIG_STM32_MEMMAP_EXT_FLASH_BASE_ADDRESS
and define the slot1 partition of the external NOR flash and as the <zephyr,chosen>

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FRASTM commented Oct 31, 2023

Example to build and link an application for the external NOR and execute it in XiP.
$ west build -p always -b stm32h735g_disco samples/boards/stm32/hello_world_xip/ --sysbuild -- -DCONFIG_FLASH_BASE_ADDRESS=0x90000000

Flashing operation is done with the STM32CubeProgrammer application or command line:

  1. $ ~/STM32CubeProgrammer/bin/STM32_Programmer_CLI -c port=swd -w32 0x08000000 0x000 -d build/mcuboot/zephyr/zephyr.hex
  2. $ ~/STM32CubeProgrammer/bin/STM32_Programmer_CLI -c port=swd -w32 0x90000000 0x000 -el ~/STM32CubeProgrammer/bin/ExternalLoader/MX25LM51245G_STM32H735G-DK.stldr -d build/with_mcuboot/zephyr/zephyr.signed.hex -rst
*** Booting Zephyr OS build zephyr-v3.5.0-656-g3d152069b087 ***
I: Starting Direct-XIP bootloader
I: Image 0 Primary slot: Image not found
I: Secondary slot: version=0.0.0+0
I: Image 0 loaded from the secondary slot
I: Bootloader chainload address offset: 0x0
I: Jumping to the image slot
*** Booting Zephyr OS build zephyr-v3.5.0-656-g3d152069b087 ***
Hello World! from external flash  stm32h735g_disco

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FRASTM commented Oct 31, 2023

It is also consist in :
west build -p always -b stm32h7b3i_dk samples/application_development/sysbuild/with_mcuboot --sysbuild -- -DCONFIG_FLASH_BASE_ADDRESS=0x90000000
and flash 2 different binary files to the 0x8000000 and 0x90000000,

  1. There must be a slot1 partition chosen to hold the image to be stored and executed in the external NOR at the defined offset (here is 0)

  2. Because of sysbuild/mcuboot.conf
    CONFIG_BOOT_UPGRADE_ONLY=y
    CONFIG_MCUBOOT_DOWNGRADE_PREVENTION=y
    The version of the image to be XiP is not set correctly :

*** Booting Zephyr OS build zephyr-v3.5.0-656-g2437cfca5cd6 ***
W: Failed reading sectors; BOOT_MAX_IMG_SECTORS=128 - too small?
W: Cannot upgrade: slots are not compatible
E: Unable to find bootable image

In case the sysbuild/mcuboot.conf
CONFIG_BOOT_UPGRADE_ONLY=n
CONFIG_MCUBOOT_DOWNGRADE_PREVENTION=n

*** Booting Zephyr OS build zephyr-v3.5.0-656-g16508f68aaf2 ***
*** Booting Zephyr OS build zephyr-v3.5.0-656-g16508f68aaf2 ***
Address of sample 0x90000000
Hello sysbuild with mcuboot! stm32h7b3i_dk

@FRASTM FRASTM force-pushed the ospi_memmap branch 12 times, most recently from 43c5947 to 6d2447b Compare November 7, 2023 13:42
@FRASTM FRASTM force-pushed the ospi_memmap branch 2 times, most recently from ca5288c to 576b7cc Compare December 12, 2023 15:13
FRASTM added 14 commits January 29, 2024 17:10
For the flash driver, the base address is the MCU internal flash
address (usualyy 0x8000000). This PR gets the that address
from the device tree node "st,stm32-nv-flash"
instead of relying on the CONFIG_FLASH_BASE_ADDRESS
which might differ when building for another flash memory.

Signed-off-by: Francois Ramu <[email protected]>
This CONFIG_STM32_MEMMAP is for enabling the MemoryMapped mode
on external octo or quad spi memory.
In this case, the flash_stm32_read is done in mem map mode
the flash_stm32_erase is not available.

Signed-off-by: Francois Ramu <[email protected]>
Enable the MemoryMapped Mode for the stm32 octoFlash driver
Configure the Flash in MemoryMapped to use in XiP mode.
With this mode the erase and write are not supported.
Address and size are given by the DTS register property.

Signed-off-by: Francois Ramu <[email protected]>
This change is aborting the memoryMapped mode of the octo-flash
before erasing or writing the NOR. Operations are performed in
command mode.
Reading is always performed in MemoryMapped mode (memcopy)

Signed-off-by: Francois Ramu <[email protected]>
Enable the DCACHE1 in INCR burt mode to allow writing to the external
NOR octoFlash when in MemoryMapped mode

Signed-off-by: Francois Ramu <[email protected]>
Define the Device tree of the b_u585i_iot02a disco kit
to access the external NOR octo-flash in MemoryMapped mode
for XiP

Signed-off-by: Francois Ramu <[email protected]>
Gives a sample to execute the little fs on external memory map
(XiP) where the lfs1 partition is in internal mcu flash
The application is built/linked/stored in the external NOR
flash on slot1 partition.

Signed-off-by: Francois Ramu <[email protected]>
Skip the PLL1 init if it is already running, this will avoid disabling
the PLL when running after a jump from mcuboot

Signed-off-by: Francois Ramu <[email protected]>
Define the MPU attribute to be ATTR_MPU_IO for the
qspi region, starting at 0x90000000 of the stm32h7 serie.

Signed-off-by: Francois Ramu <[email protected]>
Define the Device tree of the stm32h7b3i_dk disco board
to access the external NOR octo-flash in MemoryMapped mode
for XiP
Set openocd runner for debugging.

Signed-off-by: Francois Ramu <[email protected]>
Gives a sample to execute the little fs on external memory map
(XiP) where the lfs1 partition is in internal mcu flash

Signed-off-by: Francois Ramu <[email protected]>
Configures the external NOR Flash in MemoryMapped Mode, at the end of
the NOR flash-controller initialization.
Then reading/writing are performed in MemoryMapped mode
with memcopy (and no more with command mode).
In this mode: erasing is not supported anymore.
The flash size and address are given by the DTS <reg> property.

Signed-off-by: Francois Ramu <[email protected]>
Define the Device tree of the stm32l496g_disco board
or stm32h750b disco kit
to access the external NOR quad-flash in MemoryMapped mode
for XiP

Signed-off-by: Francois Ramu <[email protected]>
Gives a sample to execute the little fs on external memory map
(XiP) where the lfs1 partition is in internal mcu flash

Signed-off-by: Francois Ramu <[email protected]>
west sign accepts signing image when built and linked for
an external NOR memory (which has no write-block size property)

Signed-off-by: Francois Ramu <[email protected]>
Samples to demonstrate the XiP mode when using an external NOR flash
in MemoryMapped mode

Signed-off-by: Francois Ramu <[email protected]>
Sample to configure the octo/quad external Flash in memory Mapped mode
so that read is accessible in memecopy
Write too even if not recommended.

Signed-off-by: Francois Ramu <[email protected]>
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FRASTM commented Jan 29, 2024

not relevant anymore

Refer to #68597

@FRASTM FRASTM closed this Jan 29, 2024
@FRASTM FRASTM deleted the ospi_memmap branch February 12, 2024 08:56
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