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Add support Clock Control driver for Renesas RZ/A3UL, V2L #94948

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Add support Clock Control driver for Renesas RZ/A3UL, V2L #94948

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3cb88dc
manifest: Update commit id for hal_renesas
le-quang168 Aug 21, 2025
ddde908
drivers: clock control: Add Clock Control support for RZ/A3UL, V2L
le-quang168 Aug 14, 2025
df2a80b
dts: renesas: Add Clock Control support for RZ/A3UL, V2L
le-quang168 Aug 14, 2025
afe1e75
soc: renesas: Retrieve SYS_CLOCK_HW_CYCLES_PER_SEC from dts
le-quang168 Aug 14, 2025
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87 changes: 65 additions & 22 deletions drivers/clock_control/clock_control_renesas_rz_cpg.c
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Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,22 @@
*/

#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/renesas_rzg_clock.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <bsp_api.h>

#if defined(CONFIG_SOC_SERIES_RZG3S)
#include <zephyr/dt-bindings/clock/renesas_rzg_clock.h>
#elif defined(CONFIG_SOC_SERIES_RZA3UL)
#include <zephyr/dt-bindings/clock/renesas_rza_clock.h>
#elif defined(CONFIG_SOC_SERIES_RZV2L)
#include <zephyr/dt-bindings/clock/renesas_rzv_clock.h>
#endif

#define RZ_CLOCK_DIV(clock_id) ((clock_id & RZ_CLOCK_DIV_MASK) >> RZ_CLOCK_DIV_SHIFT)
#define RZ_CLOCK_IP(clock_id) ((clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT)
#define RZ_CLOCK_IP_CHANNEL(clock_id) ((clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT)
#define RZ_CLOCK_SRC(clock_id) ((clock_id & RZ_CLOCK_MASK) >> RZ_CLOCK_SHIFT)

#define DT_DRV_COMPAT renesas_rz_cpg

Expand All @@ -18,15 +32,15 @@ static int clock_control_renesas_rz_on(const struct device *dev, clock_control_s

uint32_t *clock_id = (uint32_t *)sys;

uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
uint32_t ip = RZ_CLOCK_IP(*clock_id);
uint32_t ch = RZ_CLOCK_IP_CHANNEL(*clock_id);

switch (ip) {
case RZ_IP_GTM:
R_BSP_MODULE_START(FSP_IP_GTM, ch);
break;
case RZ_IP_GPT:
R_BSP_MODULE_START(FSP_IP_GPT, ch);
case RZ_IP_SCI:
R_BSP_MODULE_START(FSP_IP_SCI, ch);
break;
case RZ_IP_SCIF:
R_BSP_MODULE_START(FSP_IP_SCIF, ch);
Expand All @@ -37,18 +51,32 @@ static int clock_control_renesas_rz_on(const struct device *dev, clock_control_s
case RZ_IP_RSPI:
R_BSP_MODULE_START(FSP_IP_RSPI, ch);
break;
case RZ_IP_CANFD:
R_BSP_MODULE_START(FSP_IP_CANFD, ch);
break;
#if !defined(CONFIG_SOC_SERIES_RZV2L)
case RZ_IP_ADC:
R_BSP_MODULE_START(FSP_IP_ADC, ch);
break;
case RZ_IP_WDT:
R_BSP_MODULE_START(FSP_IP_WDT, ch);
break;
#endif
#if !defined(CONFIG_SOC_SERIES_RZA3UL)
case RZ_IP_GPT:
R_BSP_MODULE_START(FSP_IP_GPT, ch);
break;
case RZ_IP_MHU:
R_BSP_MODULE_START(FSP_IP_MHU, ch);
break;
case RZ_IP_DMAC:
R_BSP_MODULE_START(FSP_IP_DMAC, ch);
break;
case RZ_IP_CANFD:
R_BSP_MODULE_START(FSP_IP_CANFD, ch);
break;
case RZ_IP_ADC:
R_BSP_MODULE_START(FSP_IP_ADC, ch);
#else
case RZ_IP_DMAC:
R_BSP_MODULE_START(FSP_IP_DMAC_NS, ch);
break;
#endif
default:
return -EINVAL; /* Invalid FSP IP Module */
}
Expand All @@ -64,15 +92,15 @@ static int clock_control_renesas_rz_off(const struct device *dev, clock_control_

uint32_t *clock_id = (uint32_t *)sys;

uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
uint32_t ip = RZ_CLOCK_IP(*clock_id);
uint32_t ch = RZ_CLOCK_IP_CHANNEL(*clock_id);

switch (ip) {
case RZ_IP_GTM:
R_BSP_MODULE_STOP(FSP_IP_GTM, ch);
break;
case RZ_IP_GPT:
R_BSP_MODULE_STOP(FSP_IP_GPT, ch);
case RZ_IP_SCI:
R_BSP_MODULE_STOP(FSP_IP_SCI, ch);
break;
case RZ_IP_SCIF:
R_BSP_MODULE_STOP(FSP_IP_SCIF, ch);
Expand All @@ -83,21 +111,36 @@ static int clock_control_renesas_rz_off(const struct device *dev, clock_control_
case RZ_IP_RSPI:
R_BSP_MODULE_STOP(FSP_IP_RSPI, ch);
break;
case RZ_IP_CANFD:
R_BSP_MODULE_STOP(FSP_IP_CANFD, ch);
break;
#if !defined(CONFIG_SOC_SERIES_RZV2L)
case RZ_IP_ADC:
R_BSP_MODULE_STOP(FSP_IP_ADC, ch);
break;
case RZ_IP_WDT:
R_BSP_MODULE_STOP(FSP_IP_WDT, ch);
break;
#endif
#if !defined(CONFIG_SOC_SERIES_RZA3UL)
case RZ_IP_GPT:
R_BSP_MODULE_STOP(FSP_IP_GPT, ch);
break;
case RZ_IP_MHU:
R_BSP_MODULE_STOP(FSP_IP_MHU, ch);
break;
case RZ_IP_DMAC:
R_BSP_MODULE_STOP(FSP_IP_DMAC, ch);
break;
case RZ_IP_CANFD:
R_BSP_MODULE_STOP(FSP_IP_CANFD, ch);
break;
case RZ_IP_ADC:
R_BSP_MODULE_STOP(FSP_IP_ADC, ch);
#else
case RZ_IP_DMAC:
R_BSP_MODULE_STOP(FSP_IP_DMAC_NS, ch);
break;
#endif
default:
return -EINVAL; /* Invalid */
return -EINVAL; /* Invalid FSP IP Module */
}

return 0;
}

Expand All @@ -110,8 +153,8 @@ static int clock_control_renesas_rz_get_rate(const struct device *dev, clock_con

uint32_t *clock_id = (uint32_t *)sys;

fsp_priv_clock_t clk_src = (*clock_id & RZ_CLOCK_MASK) >> RZ_CLOCK_SHIFT;
uint32_t clk_div = (*clock_id & RZ_CLOCK_DIV_MASK) >> RZ_CLOCK_DIV_SHIFT;
fsp_priv_clock_t clk_src = RZ_CLOCK_SRC(*clock_id);
uint32_t clk_div = RZ_CLOCK_DIV(*clock_id);

uint32_t clk_hz = R_FSP_SystemClockHzGet(clk_src);
*rate = clk_hz / clk_div;
Expand Down
134 changes: 134 additions & 0 deletions dts/arm/renesas/rz/rzv/r9a07g054.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@
#include <mem.h>
#include <freq.h>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/clock/renesas_rzv_clock.h>
#include <zephyr/dt-bindings/i2c/i2c.h>

/ {
Expand All @@ -33,6 +34,12 @@
};
};

osc: osc {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(24)>;
#clock-cells = <0>;
};

soc {
adc: adc@40059000 {
compatible = "renesas,rz-adc-c";
Expand All @@ -45,6 +52,133 @@
status = "disabled";
};

cpg: clock-controller@41010000 {
compatible = "renesas,rz-cpg";
reg = <0x41010000 DT_SIZE_K(64)>;
#clock-cells = <1>;
status = "okay";

iclk: iclk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(1200)>;
#clock-cells = <0>;
};

i2clk: i2clk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(200)>;
#clock-cells = <0>;
};

gclk: gclk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(500)>;
#clock-cells = <0>;
};

s0clk: s0clk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_K(12)>;
#clock-cells = <0>;
};

spi0clk: spi0clk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(200)>;
#clock-cells = <0>;
};

spi1clk: spi1clk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(100)>;
#clock-cells = <0>;
};

sd0clk: sd0clk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(533)>;
#clock-cells = <0>;
};

sd1clk: sd1clk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(533)>;
#clock-cells = <0>;
};

m0clk: m0clk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(200)>;
#clock-cells = <0>;
};

m1clk: m1clk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(3000)>;
#clock-cells = <0>;
};

m2clk: m2clk {
compatible = "fixed-clock";
clock-frequency = <266500000>;
#clock-cells = <0>;
};

m3clk: m3clk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(3000)>;
#clock-cells = <0>;
};

m4clk: m4clk {
compatible = "fixed-clock";
clock-frequency = <16656000>;
#clock-cells = <0>;
};

hpclk: hpclk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(250)>;
#clock-cells = <0>;
};

tsuclk: tsuclk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(80)>;
#clock-cells = <0>;
};

ztclk: ztclk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(100)>;
#clock-cells = <0>;
};

p0clk: p0clk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(100)>;
#clock-cells = <0>;
};

p1clk: p1clk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(200)>;
#clock-cells = <0>;
};

p2clk: p2clk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(100)>;
#clock-cells = <0>;
};

atclk: atclk {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(400)>;
#clock-cells = <0>;
};
};

pinctrl: pin-controller@41030000 {
compatible = "renesas,rzv-pinctrl";
reg = <0x41030000 DT_SIZE_K(64)>;
Expand Down
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