Improve targets.

Author: AngelTerrones

Makefile

@@ -5,6 +5,7 @@ SHELL=bash
 .PYTEST=pytest
 
 .RTL_FOLDER=$(shell cd rtl; pwd)
+.VERILOG_FILES=$(shell find $(.RTL_FOLDER) -name "*.v")
 .TEST_FOLDER=$(shell cd test; pwd)
 .SCRIPT_FOLDER=$(shell cd scripts; pwd)
 
@@ -40,19 +41,16 @@ test_alu: check_alu
 # ********************************************************************
 # Implementation
 # ********************************************************************
-build-bitstream: $(.FOUT)/$(.BIT_FOLDER)/$(.PROJECT_NAME).bit
-
-build-prom: build-bitstream $(.FOUT)/$(.BIT_FOLDER)/$(.PROJECT_NAME).mcs
+build-prom: $(.FOUT)/$(.BIT_FOLDER)/$(.PROJECT_NAME).mcs
 
 program-fpga: build-prom
 	@$(.SCRIPT_FOLDER)/program_fpga.sh $(.PROJECT_NAME) $(.BIT_FOLDER) $(.FOUT)
 
-$(.FOUT)/$(.BIT_FOLDER)/$(.PROJECT_NAME).bit: ucf/pines.ucf
+# ---
+$(.FOUT)/$(.BIT_FOLDER)/$(.PROJECT_NAME).mcs: $(.VERILOG_FILES) ucf/pines.ucf
 	@mkdir -p $(.FOUT)
 	@$(.SCRIPT_FOLDER)/create_project.sh $(.RTL_FOLDER) $(.FOUT) $(.PROJECT_NAME)
 	@$(.SCRIPT_FOLDER)/create_bitstream.sh $(.FPGA) $(.FOUT) $(.BIT_FOLDER) $(.PROJECT_NAME) $(.TOPE_V)
-
-$(.FOUT)/$(.BIT_FOLDER)/$(.PROJECT_NAME).mcs:
 	@$(.SCRIPT_FOLDER)/generate_prom_file.sh $(.PROJECT_NAME) $(.BIT_FOLDER) $(.FOUT)
 
 # ********************************************************************

rtl/driver7seg.v

@@ -38,4 +38,4 @@ end
 endmodule
 // ****************************************************************************
 // EOF
-// ****************************************************************************
+// ****************************************************************************

scripts/create_bitstream.sh

@@ -24,24 +24,15 @@ if [ $# -ne $EXPECTED_ARGS ]; then
     exit 1
 fi
 
-#-------------------------------------------------------------------------------
-# folders
-#-------------------------------------------------------------------------------
-BUILD_FOLDER=$2
-
 #-------------------------------------------------------------------------------
 # move to workspace
 #-------------------------------------------------------------------------------
-cd $BUILD_FOLDER
+cd $2
 
 #-------------------------------------------------------------------------------
-# create link to UCF file
+# copy UCF, xst_verilog, and configure xst file
 #-------------------------------------------------------------------------------
 cp -f ../ucf/pines.ucf $4.ucf
-
-#-------------------------------------------------------------------------------
-# copy xst_verilog and configure
-#-------------------------------------------------------------------------------
 cp ../scripts/xst_verilog.opt .
 sed -i "s/TOPE/$5/g" ./xst_verilog.opt
 

scripts/create_project.sh

@@ -22,11 +22,6 @@ if [ $# -ne $EXPECTED_ARGS ]; then
     exit 1
 fi
 
-#-------------------------------------------------------------------------------
-# Hardware folder
-#-------------------------------------------------------------------------------
-RTL_FOLDER=$1
-
 #-------------------------------------------------------------------------------
 # File project
 #-------------------------------------------------------------------------------
@@ -40,7 +35,7 @@ touch $FILE_PROJECT
 
 unamestr=`uname`
 
-for module in $RTL_FOLDER; do
+for module in $1; do
     for file in $(find $module -name "*.v")
     do
     if [[ "$unamestr" == 'Linux' ]]; then