Graduate student in Computer Engineering with expertise in SoC and ASIC design for high-performance machine learning acceleration. Strong focus on RTL development, RISC-based processor architectures for SoC integration, and performance-optimized hardware implementations.
💡 Interests
- RTL Design and IP Integration Targeting Machine Learning Workloads
- Processor Microarchitecture Integration
🛠️ Skilled In:
- RTL Design (Verilog/SystemVerilog)
- Front-end static verification (Linting, CDC, RDC, X-Propagation, FSM validation, Pipeline hazards, Memory consistency, Clock gating.)
- Functional & Formal Verification (Assertions, Properties)
- Logic Synthesis & Static Timing Analysis (STA)
- Verilog/SystemVerilog, C/C++, MATLAB
- Python (for automation, ML workflows)
- Cadence (Genus, Innovus, Spectre), Synopsys Design Compiler
- VS Code, ModelSim, GTKWave
- Git, CMake, Make, Shell scripting
- Advanced Microarchitecture Design and Verification
- UVM, Formal Methods, and Equivalence Checking
- System-Level Simulation and Co-Design
- DevOps and Toolchain Automation for Hardware Projects