This repository contains small Verilog modules and schematics demonstrating fundamental concepts in digital design and VLSI.
verilogBasics/– Simple “Hello world” programs for learning Verilog syntax (datatypes, operators, slicing, etc.). Each folder contains simulation scripts.combinatorialCircuits/– Examples such as adders, subtractors, encoders, decoders, comparators, multiplexers, and a simple ALU. Many subfolders include ModelSim TCL scripts for running simulations.sequentialCircuits/– Clock‑related designs (e.g.,clockGenAndDist) with a detailed README describing clock division, gating, DLL/CDR concepts, and more.schematics_basic_gates/– Cadence schematics and testbenches for gates like NAND, NOR, XOR, and basic circuits such as inverters and ring oscillators.