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3629ff2
fix(repo): keep SDD reports untracked
Aug 5, 2026
14b642a
fix(tool): scope bytecode probe to public driver
Aug 5, 2026
2462507
feat(lowering): plan process continuation control flow
Aug 5, 2026
33f1de5
feat(lowering): plan typed live state and emissions
Aug 6, 2026
5e10946
feat(lowering): bound and atomically publish process plans
Aug 6, 2026
2e0a4ca
feat(lowering): expose canonical process-state reports
Aug 6, 2026
fd92b23
feat(lowering): plan ACSim process state
Aug 6, 2026
125a72a
feat(gfsim): C++20 event-driven simulator runtime foundation
Aug 6, 2026
4efa785
test(gfsim): expand coverage to 57 tests with edge cases, invariants,…
Aug 6, 2026
8ce3f99
feat(codegen): deterministic C++ code generation with fingerprints an…
Aug 6, 2026
f28ef12
build: add ASAN and UBSAN CMake presets
Aug 6, 2026
d44406d
feat(gfsim): add baseline component library header
Aug 6, 2026
57e07c5
test(ir): add per-op valid+invalid coverage audit script
Aug 6, 2026
b20ec11
test(ir): add missing invalid coverage for 8 operations
Aug 6, 2026
de694e5
build(lowering): scaffold ACIR-to-ACSim conversion pass infrastructure
Aug 6, 2026
746d74a
fix(test): align negative lit tests with enforced verifier diagnostics
Aug 6, 2026
a67c079
wip(lowering): draft ACIR-to-ACSim structural conversion (incomplete)
Aug 6, 2026
63af90e
fix(build): link ACIRToACSim into acir-opt drivers
Aug 6, 2026
1bf4876
fix(lowering): make conversion-pass scaffold build and register cleanly
Aug 6, 2026
7f695b6
Merge branch 'wip/acir-to-acsim-lowering' into feature/acir-acsim
Aug 6, 2026
39b9946
feat(lowering): atomically lower ACIR to ACSim
Aug 6, 2026
bfda550
test(lowering): add atomic negative conversion coverage and conversio…
Aug 7, 2026
28937ae
test(ir): enforce complete ACIR and ACSim coverage
Aug 7, 2026
3c8399e
test(ir): cover the 256-relation mixed-interleave capability limit
Aug 7, 2026
6b7c222
style: reconcile NOLINT suppressions with the clang-format gate
Aug 7, 2026
87ee0da
docs(audit): record the Phase 1 completion audit
Aug 7, 2026
17e21dc
fix(lowering): use explicit zero-inline SmallVector for PlacementPlan
Aug 8, 2026
88edd8f
build: compile MLIR-facing targets with -fno-rtti when LLVM has none
Aug 8, 2026
56ac288
ci: build the lit substitution tools into the cached LLVM build
Aug 8, 2026
85a7ee1
ci: run the dev lit suite verbosely so failures print bodies
Aug 9, 2026
f32e27e
ci: cache the LLVM build even when tests fail
Aug 9, 2026
42b155d
test(contracts): cover the restore/save LLVM cache split
Aug 9, 2026
6b2bcfd
docs(plan): draft the Phase 2 gfsim runtime implementation plan
Aug 9, 2026
bbb66b3
docs(plan): repair Phase 1 review blockers
Aug 10, 2026
c55c77c
fix(analysis): publish complete process-state planning
Aug 10, 2026
165ef02
docs(plan): include private planner state repair
Aug 10, 2026
e4d7f49
fix(analysis): preserve branch control and path fairness
Aug 10, 2026
78d6c53
fix(lowering): topologically order module realizations
Aug 10, 2026
8a93d7b
fix(lowering): preserve frozen hierarchy paths
Aug 10, 2026
341fe79
fix(lowering): fingerprint canonical realization content
Aug 10, 2026
3d845a8
fix(lowering): emit planned process state machines
Aug 10, 2026
c3fc5ec
fix(lowering): verify before atomic publication
Aug 10, 2026
c0f24c5
fix(lowering): emit pure results and exports
Aug 10, 2026
acad3e4
fix(lowering): emit typed graph activation edges
Aug 10, 2026
7d4df29
fix(lowering): complete composite whole-model emission
Aug 10, 2026
8d599c1
fix(lowering): preserve typed process captures
Aug 10, 2026
e929fd9
fix(cmake): export the complete public surface
Aug 10, 2026
940b981
fix(lowering): publish scalar storage wrappers
Aug 10, 2026
fd3326c
fix(cmake): link ACSim control-flow dependency
Aug 10, 2026
65aabec
docs(audit): certify repaired Phase 1 baseline
Aug 10, 2026
aae7681
feat(gfsim): add deterministic static scheduler dispatch
Aug 10, 2026
daecfbb
feat(gfsim): add static activation adjacency
Aug 10, 2026
0fc6b90
feat(gfsim): enforce deterministic resource arbitration
Aug 10, 2026
0584a09
feat(gfsim): add bounded process runtime
Aug 10, 2026
2ac5ada
feat(gfsim): complete baseline component templates
Aug 10, 2026
f5c4b59
feat(gfsim): enforce protocol and packet invariants
Aug 10, 2026
054f765
feat(gfsim): add PTO trace streaming cursor
Aug 10, 2026
b0bfed9
feat(gfsim): add no-progress diagnostics and statistics
Aug 10, 2026
660fbc5
feat(stdlib): publish frozen component catalog
Aug 10, 2026
602db11
ci: add gfsim sanitizer matrix
Aug 10, 2026
29064b7
fix(gfsim): close phase 2 audit gaps
Aug 10, 2026
8ec1c7b
docs(audit): certify phase 2 runtime baseline
Aug 10, 2026
bcb41cd
docs(design): define phase 3 code generation
Aug 10, 2026
3b558d4
docs(plan): define phase 3 implementation
Aug 10, 2026
c3ef6ca
feat(codegen): enforce exact build manifest
Aug 10, 2026
1d09f09
feat(gfsim): attach non-owning module children
Aug 10, 2026
9937126
feat(codegen): extract canonical model plan
Aug 10, 2026
217e870
feat(codegen): model hierarchy and process plans
Aug 10, 2026
03cfc33
feat(codegen): generate typed module sources
Aug 10, 2026
4b4f053
feat(codegen): emit enum pc processes
Aug 10, 2026
d241a48
feat(codegen): emit static model harness
Aug 10, 2026
13926ce
feat(codegen): plan same toolchain builds
Aug 10, 2026
ee65966
feat(codegen): publish immutable generated builds
Aug 10, 2026
1187a72
feat(codegen): add internal cxx generation driver
Aug 10, 2026
746e4cd
test(codegen): enforce phase 3 conformance
Aug 10, 2026
2bf6b54
fix(codegen): close hierarchical generation contracts
Aug 10, 2026
0b1ee58
fix(codegen): make sanitizer build tests hermetic
Aug 10, 2026
6e89c15
docs(audit): complete phase 3 verification
Aug 10, 2026
ce406c0
merge: complete phase 3 binding and codegen
Aug 10, 2026
9ccb34c
docs(audit): record phase 3 integration
Aug 10, 2026
c6f27a5
docs(design): define phase 4 python and cli architecture
Aug 11, 2026
40da285
docs(plan): prepare phase 4 frontend and cli execution
Aug 11, 2026
61fd46f
feat(python): add exact frontend public types
Aug 11, 2026
7b25a3d
feat(frontend): index source and order diagnostics
Aug 11, 2026
42100af
feat(frontend): validate and evaluate static Python
Aug 11, 2026
851f69e
feat(acpy): add closed semantic document contract
Aug 11, 2026
b4980e5
feat(frontend): capture definitions and schema calls
Aug 11, 2026
a6f840c
feat(frontend): normalize SSA and resolve component calls
Aug 11, 2026
a0424c8
feat(frontend): outline scopes and canonicalize collections
Aug 11, 2026
b63b690
feat(frontend): add protocol resource and address semantics
Aug 11, 2026
6cb38a9
feat(frontend): construct supported process CFGs
Aug 11, 2026
7784864
feat(frontend): lower verified ACPy to canonical ACIR
Aug 11, 2026
f22d30e
feat(codegen): preserve frontend process control flow
Aug 11, 2026
d28e84a
docs(audit): complete phase 4a frontend verification
Aug 11, 2026
4f0015c
feat(compiler): add high-level native driver facade
Aug 11, 2026
10b0aa0
feat(python): bridge frontend to native compiler
Aug 11, 2026
c1d77d8
feat(cli): add workspace parser and output policy
Aug 11, 2026
5696a92
feat(cli): add schema capability and doctor discovery
Aug 11, 2026
55d2461
feat(cli): add isolated check and elaborate commands
Aug 11, 2026
07f9ac3
feat(cli): add deterministic compile stages
Aug 11, 2026
91b18e9
feat(cli): build with exact frontend provenance
Aug 11, 2026
2b5e30e
feat(runtime): execute immutable run manifests
Aug 11, 2026
a790b70
feat(cli): run and replay immutable manifests
Aug 11, 2026
36d9940
feat(cli): add deterministic architecture inspection
Aug 11, 2026
c923d4c
test(cli): gate commands installation and determinism
Aug 11, 2026
82d14fa
test(cli): cover every public exit code
Aug 11, 2026
6583bba
docs(audit): complete phase 4 python and cli verification
Aug 11, 2026
70236fd
docs(design): define phase 5 end-to-end NPU delivery
Aug 11, 2026
6697cc8
docs(plan): prepare phase 5 end-to-end NPU execution
Aug 11, 2026
b5f21f9
feat(trace): add strict DavinciOO trace adapter
Aug 11, 2026
927a23e
feat(trace): add explicit DavinciOO import command
Aug 11, 2026
1ec354d
feat(gfsim): record committed runtime observations
Aug 11, 2026
1629a1a
feat(runtime): publish committed statistics and events
Aug 11, 2026
daf036d
feat(runtime): inject validated PTO traces into generated models
Aug 11, 2026
4cbfa79
feat(trace): add deterministic Perfetto event packer
Aug 11, 2026
ef1ffe0
feat(gfsim): instrument baseline component commits
Aug 11, 2026
88d1b96
feat(examples): add deterministic Phase 5 showcase models
Aug 11, 2026
cfe423f
test(e2e): add six Phase 5 pipeline goldens
Aug 11, 2026
0923fcc
feat(npu): add typed PTO instruction decode
Aug 11, 2026
23e0906
feat(npu): schedule dependency-aware oldest-ready work
Aug 11, 2026
c0763c4
feat(npu): execute and retire superscalar instructions
Aug 11, 2026
2f412b0
feat(npu): add hierarchical end-to-end showcase
Aug 11, 2026
4d79202
test(phase5): close determinism and replay coverage
Aug 11, 2026
ecfba53
docs(audit): record phase 5 completion evidence
Aug 11, 2026
e358074
fix: address phase 5 review findings
Aug 11, 2026
6418cb8
merge: complete phase 5 end-to-end NPU
Aug 11, 2026
18dbcca
feat(examples): add DavinciOO gfsim reference model
Aug 24, 2026
b9cccf2
merge: add DavinciOO gfsim reference model
Aug 24, 2026
5f512f6
docs(spec): propose v0.2 Queue/Var architecture manual
Aug 24, 2026
b52c223
docs(plan): start v0.2 Queue/Var upgrade
Aug 24, 2026
278ac08
feat(acir): add v0.2 Queue and Var types
Aug 24, 2026
55d9b4c
feat(acir): add static Queue and Var collections
Aug 24, 2026
2171fc6
feat(acir): add typed transform building block
Aug 24, 2026
64016f1
feat(acir): define atomic Queue firing effects
Aug 24, 2026
f968bea
feat(acir): add typed source and sink blocks
Aug 24, 2026
73c8dd6
feat(python): lower simple serial Queue pipelines
Aug 24, 2026
9de3900
feat(acir): add immutable Var expression blocks
Aug 24, 2026
1568dd9
feat(python): lower immutable struct lambdas
Aug 24, 2026
524bdb5
feat(acir): add inferred Queue scope boundaries
Aug 24, 2026
da462d3
feat(python): infer nested Queue scope boundaries
Aug 24, 2026
1ee11d3
feat(acir): add strict typed broadcast block
Aug 24, 2026
1800de4
feat(python): infer strict Queue broadcast
Aug 24, 2026
a9f85af
feat(python): place broadcast across Queue scopes
Aug 24, 2026
283695a
feat(acir): add typed runtime route block
Aug 24, 2026
8b14fbf
feat(python): lower typed Queue routes
Aug 24, 2026
8eba4e3
feat(python): flatten static Queue collections
Aug 24, 2026
bbab582
feat(acir): add merge and bounded feedback blocks
Aug 24, 2026
481ab50
feat(python): lower serial while to bounded feedback
Aug 24, 2026
b4582aa
feat(python): lower typed Queue merges
Aug 24, 2026
0f4f56d
feat(gfsim): add typed Queue building blocks
Aug 24, 2026
4231951
feat(gfsim): generate typed Queue C++ from Python
Aug 24, 2026
3341100
feat(gfsim): add Queue topology blocks
Aug 24, 2026
f6871c1
feat(gfsim): generate route merge and feedback blocks
Aug 24, 2026
e15645e
feat(gfsim): generate strict Queue broadcasts
Aug 24, 2026
f4ece3d
feat(gfsim): generate nested SimQueue arrays
Aug 24, 2026
6cedd3e
feat(gfsim): generate inferred Queue hierarchy
Aug 24, 2026
9d6555b
feat(example): generate DavinciOO-like Queue model
Aug 24, 2026
5ef1d43
feat(acir): freeze Queue logical identities
Aug 24, 2026
9993ca8
feat(codegen): extract canonical QueueGraph plan
Aug 24, 2026
e2e430c
feat(codegen): generate Queue C++ from frozen ACIR
Aug 24, 2026
184a286
feat(codegen): emit broadcast and feedback from ACIR
Aug 24, 2026
f4a0123
feat(pyc): lower scalar Queue pipeline to Verilog
Aug 24, 2026
b82d7fc
feat(pyc): flatten structs and verify refinement
Aug 24, 2026
f8498a5
feat(pyc): lower Queue topology and arbitration
Aug 24, 2026
e55351d
feat(queue): add observation-only uses and graph checks
Aug 24, 2026
28fa298
feat(queue): add atomic firing and exact latency lowering
Aug 24, 2026
f1429e2
feat(python): add static control and explicit widths
Aug 24, 2026
2821c01
feat(queue): add decoupled fork building block
Aug 24, 2026
b426047
docs(spec): add Queue Var v0.2 manual
Aug 24, 2026
ec556a1
test(acir): refresh v0.2 opcode registry coverage
Aug 24, 2026
aed3592
refactor(contract): remove ac.std namespace
Aug 24, 2026
0507308
feat(contract): hard break global epoch to 0.2
Aug 24, 2026
2da0640
feat(python): lower runtime if to Queue topology
Aug 24, 2026
99f64d0
feat(pyc): lower bounded Queue feedback
Aug 24, 2026
e82e5c1
feat(acir): freeze official Queue block catalog
Aug 24, 2026
d9fa59b
feat(acir): add ordered retirement and DavinciOO gate
Aug 24, 2026
a7e285a
feat(acir): add explicit dependency scheduling
Aug 24, 2026
d9d9a86
feat(acir): enforce dependency resource reservation
Aug 24, 2026
0d202bc
feat(acir): add typed queue memory
Aug 24, 2026
47e9108
feat(acir): add credit and barrier scheduling
Aug 24, 2026
1af661f
feat(acir): add static queue collection select
Aug 24, 2026
40134a0
feat(acpy): add explicit queue firing effects
Aug 24, 2026
3ef228d
feat(acpy): lower bounded loop control
Aug 24, 2026
6135770
feat(acir): enforce verification role placement
Aug 24, 2026
b82d92f
test(v0.2): close upgrade audit
Aug 24, 2026
667f22c
Merge pull request #12 from PTO-ISA/codex/v0.2-queue-var-upgrade
zhoubot Aug 24, 2026
e947f3b
build: enable PIC for installed static libraries
Aug 24, 2026
2c5bf77
build: align gfsim RTTI with LLVM
Aug 24, 2026
f0a43f2
build: fix generated model Linux portability
Aug 24, 2026
3b5b018
docs(v0.2): add teammate specification manual
Aug 24, 2026
5fda2b9
build: derive LLVM runtime link flags
Aug 24, 2026
f96f12f
build: resolve LLVM link target closure
Aug 24, 2026
319bc1d
test: share generated model toolchain closure
Aug 24, 2026
64fdb2f
fix(gfsim): preserve optional trace identities
Aug 24, 2026
e14fcdb
fix: satisfy full clang-tidy gate
Aug 24, 2026
ae8e1bd
ci: restore sanitizer build prerequisites
Aug 24, 2026
b3ddbd4
test: align sanitizer RTTI mode
Aug 24, 2026
d35b1fb
fix(codegen): keep time domains runtime-constant
Aug 24, 2026
6b6c68c
test: propagate RTTI mode to generated models
Aug 24, 2026
07f604c
Merge pull request #13 from PTO-ISA/codex/v0.2-queue-var-upgrade
zhoubot Aug 24, 2026
dcb9945
feat(v0.3): add parameterized block JIT vertical slice
Aug 26, 2026
d8a0da5
feat(gfsim): specialize high-level block templates
Aug 26, 2026
b56a9bc
fix(v0.3): separate scheduling from engine execution
Aug 26, 2026
4ae9b88
feat(jit): preserve specialization identity in frozen artifacts
Aug 26, 2026
d8920d4
feat(v0.3): add optimized compute and pipeline blocks
Aug 26, 2026
490cdb8
feat(queue): add frozen multi-rate gfsim contract
Aug 26, 2026
72501a0
fix(queue): require rate to fit queue depth
Aug 26, 2026
fcb877d
feat: lower round-robin merge to qualified PYC arbiter
Aug 26, 2026
e964872
feat: add PYC-compatible Verilog backend
Aug 27, 2026
605411b
fix: register var popcount in ACIR coverage
Aug 27, 2026
52a3c0e
style: format ACIR and PYC lowering changes
Aug 27, 2026
7a437a8
test: match arbiter PYC attributes on one line
Aug 27, 2026
52579ad
test: follow arbiter attribute emission order
Aug 27, 2026
99a251d
feat: add explicit memory instances for epoch v0.3
hmljy2020 Aug 27, 2026
fb62341
test: update ACIR registry expectations for var popcount
Aug 27, 2026
548587a
feat: add memory latency and static bank workflows
hmljy2020 Aug 27, 2026
4f5d8c0
fix(v0.3): close explicit memory review gaps
Aug 27, 2026
ce59021
Merge pull request #20 from hmljy2020/codex/explicit-memory-v03
zhoubot Aug 27, 2026
e804633
Merge remote-tracking branch 'origin/main' into codex/v0.3-parameteri…
Aug 27, 2026
5514f88
feat(v0.3): run DavinciOO PTO trace and emit swimlane
Aug 27, 2026
b2773e7
merge main and harden PYC Verilog backend
Aug 28, 2026
942d436
style: restore repository clang-format compliance
Aug 28, 2026
79102e9
test: update deterministic compile artifact hash
Aug 28, 2026
87d5c7c
Merge pull request #19 from PTO-ISA/feature/issue11-pyc-backend-mvp
zhoubot Aug 28, 2026
ae7311b
test: refresh phase5 NPU schema fingerprints
Aug 28, 2026
9125577
Merge pull request #21 from PTO-ISA/feature/issue11-pyc-backend-mvp
zhoubot Aug 28, 2026
c1ee668
refactor: adopt release-neutral repository layout
Aug 28, 2026
73e2432
Merge origin/main into release-neutral layout
Aug 28, 2026
f40faf7
ci: align formatting gate with references layout
Aug 28, 2026
84f8d38
ci: update hard-break workspace paths
Aug 28, 2026
756002e
Merge pull request #22 from PTO-ISA/codex/v0.3-parameterized-blocks-jit
zhoubot Aug 28, 2026
386d10a
chore(acir): import Agentic Circuit history
Aug 31, 2026
0413cf1
docs(governance): define Agentic Circuit consolidation
Aug 31, 2026
8a329ac
feat(acir): integrate ACIR with the pyc6 toolchain
Aug 31, 2026
7caeec1
docs(acir): publish unified repository workflow
Aug 31, 2026
b6ebc50
docs(acir): record migrated collaboration items
Aug 31, 2026
f90ede8
build(acir): close the integrated install and gate flow
Aug 31, 2026
e6be97b
chore(acir): isolate component lint policy
Aug 31, 2026
d546b8c
fix(linx): normalize legacy commit trace fixtures
Aug 31, 2026
83f7f74
docs(gates): record Agentic Circuit implementation status
Aug 31, 2026
ff8da8c
docs(gates): archive Agentic Circuit consolidation evidence
Aug 31, 2026
de13c63
chore(gates): normalize archived evidence
Aug 31, 2026
a70d06e
docs(acir): refresh the pyc6 integration diagram
Aug 31, 2026
563b604
docs(gates): verify Agentic Circuit consolidation
Aug 31, 2026
14bc9a4
Revert "fix(linx): normalize legacy commit trace fixtures"
Aug 31, 2026
4c07b29
docs(ac): separate consolidation from repository retirement
Aug 31, 2026
d438336
style(frontend): trim imported whitespace
Aug 31, 2026
b6292b5
docs(ac): close completed consolidation plan items
Aug 31, 2026
698b7f3
style(frontend): satisfy current lint hooks
Aug 31, 2026
67bb3f2
revert: avoid unrelated frontend reformat
Aug 31, 2026
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5 changes: 5 additions & 0 deletions .github/CODEOWNERS
Original file line number Diff line number Diff line change
Expand Up @@ -7,3 +7,8 @@
/CONTRIBUTING.md @PTO-ISA/pycircuit-maintainers
/SECURITY.md @PTO-ISA/pycircuit-maintainers
/CODE_OF_CONDUCT.md @PTO-ISA/pycircuit-maintainers

# Agentic Circuit remains a separate semantic and package boundary in the
# shared repository, but follows the same maintainer review authority.
/components/agentic-circuit/ @PTO-ISA/pycircuit-maintainers
/docs/acir/ @PTO-ISA/pycircuit-maintainers
7 changes: 5 additions & 2 deletions .pre-commit-config.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -6,24 +6,27 @@ repos:
- id: check-yaml
args: [--unsafe]
- id: end-of-file-fixer
exclude: ^components/agentic-circuit/
- id: trailing-whitespace
exclude: ^components/agentic-circuit/

- repo: https://github.com/astral-sh/ruff-pre-commit
rev: v0.11.8
hooks:
- id: ruff
exclude: ^(designs/XiangShan-pyc/|designs/outerCube/|designs/BypassUnit/|designs/RegisterFile/)
exclude: ^(components/agentic-circuit/|designs/XiangShan-pyc/|designs/outerCube/|designs/BypassUnit/|designs/RegisterFile/)

- repo: https://github.com/psf/black
rev: 24.10.0
hooks:
- id: black
exclude: ^components/agentic-circuit/

- repo: https://github.com/DavidAnson/markdownlint-cli2
rev: v0.18.1
hooks:
- id: markdownlint-cli2
exclude: ^(docs/gates/logs/|designs/outerCube/.*\.md$|designs/XiangShan-pyc/docs/design_hierarchy_plan\.md$|docs/cycle_balance_improvement.*\.md$)
exclude: ^(components/agentic-circuit/|docs/gates/logs/|designs/outerCube/.*\.md$|designs/XiangShan-pyc/docs/design_hierarchy_plan\.md$|docs/cycle_balance_improvement.*\.md$)

- repo: local
hooks:
Expand Down
20 changes: 20 additions & 0 deletions CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,8 @@ include(GNUInstallDirs)

option(PYC_BUILD_MLIR_TOOLS "Build MLIR-based pyc tools" ON)
option(PYC_BUILD_RUNTIME_LIB "Build pyc6 runtime library" ON)
option(PYC_BUILD_AGENTIC_CIRCUIT "Build the integrated Agentic Circuit component" OFF)
option(PYC_BUILD_AGENTIC_CIRCUIT_TESTS "Build Agentic Circuit tests" OFF)
option(PYC_RUNTIME_ENABLE_ZLIB_TRACE "Enable gzip trace output in runtime (optional)" OFF)
option(PYC_RUNTIME_BUILD_SHARED "Build shared pyc6 runtime library" OFF)
option(PYC_INSTALL_TEMPLATES "Install runtime template libraries" ON)
Expand Down Expand Up @@ -34,6 +36,13 @@ if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/.git")
endif()
endif()

if(PYC_BUILD_AGENTIC_CIRCUIT)
# Discover LLVM/MLIR in the common parent scope so the PYC and ACIR sibling
# subprojects share one imported target graph.
find_package(LLVM 22.1.8 EXACT CONFIG REQUIRED)
find_package(MLIR 22.1.8 EXACT CONFIG REQUIRED)
endif()

if(PYC_BUILD_MLIR_TOOLS)
add_subdirectory(compiler/mlir)
endif()
Expand All @@ -42,6 +51,17 @@ if(PYC_BUILD_RUNTIME_LIB)
add_subdirectory(runtime/cpp)
endif()

if(PYC_BUILD_AGENTIC_CIRCUIT)
if(NOT PYC_BUILD_MLIR_TOOLS OR NOT PYC_BUILD_RUNTIME_LIB)
message(FATAL_ERROR
"PYC_BUILD_AGENTIC_CIRCUIT requires PYC_BUILD_MLIR_TOOLS=ON and "
"PYC_BUILD_RUNTIME_LIB=ON so ACIR-to-PYC uses the repo-local pyc6 toolchain")
endif()
set(ACIR_BUILD_TESTING "${PYC_BUILD_AGENTIC_CIRCUIT_TESTS}" CACHE BOOL
"Build Agentic Circuit tests" FORCE)
add_subdirectory(components/agentic-circuit)
endif()

if(PYC_INSTALL_TEMPLATES)
install(
DIRECTORY runtime/cpp
Expand Down
2 changes: 1 addition & 1 deletion LICENSE
Original file line number Diff line number Diff line change
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BSD 3-Clause License

Copyright (c) 2026, Kevin Zhou
Copyright (c) 2026, PTO-ISA

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
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63 changes: 54 additions & 9 deletions README.md
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# pyCircuit 6

<p align="center">
<img src="https://img.shields.io/badge/License-MIT-blue.svg" alt="License">
<img src="https://img.shields.io/badge/License-BSD--3--Clause-blue.svg" alt="License">
<img src="https://img.shields.io/badge/Python-3.10%2B-green.svg" alt="Python">
<img src="https://img.shields.io/badge/MLIR-22-orange.svg" alt="MLIR">
<a href="https://github.com/PTO-ISA/pyCircuit/actions"><img src="https://github.com/PTO-ISA/pyCircuit/actions/workflows/ci.yml/badge.svg" alt="CI"></a>
<a href="https://github.com/PTO-ISA/pyCircuit/actions/workflows/release.yml"><img src="https://github.com/PTO-ISA/pyCircuit/actions/workflows/release.yml/badge.svg" alt="Release"></a>
<a href="https://github.com/PTO-ISA/pyCircuit/releases"><img src="https://img.shields.io/github/v/release/PTO-ISA/pyCircuit?display_name=tag" alt="Latest release"></a>
</p>

pyCircuit is a Python hardware construction language. It lowers cycle-aware
designs to a verified MLIR dialect, then emits synthesizable Verilog and a C++
cycle model from the same IR.
pyCircuit is a Python hardware construction and architecture-modeling
repository. The `pycircuit` frontend lowers cycle-aware designs to verified PYC
MLIR and emits synthesizable Verilog and a C++ cycle model. The retained
`agentic_circuit` frontend lowers architecture/process/queue descriptions to
ACIR, then targets either ACSim/gfsim or the pyCircuit 6 hardware flow.

[`PTO-ISA/pyCircuit`](https://github.com/PTO-ISA/pyCircuit) is the canonical
repository, release authority, and only source of truth.
repository, release authority, and only active source of truth for both
pyCircuit and Agentic Circuit.
[`LinxISA/pyCircuit`](https://github.com/LinxISA/pyCircuit) is its downstream
fork for Linx integration work.

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bash flows/scripts/pyc build
```

The Agentic Circuit frontend remains a separate distribution and Python
namespace in the same source repository:

```bash
python3 -m pip install -e components/agentic-circuit
agentic-circuit --help
```

Release wheels, once published, use the distribution name `pycircuit-hisi`;
the Python import remains `pycircuit`. The repository does not claim a PyPI
release until the corresponding PTO-ISA release workflow has completed.
Expand All @@ -51,6 +62,24 @@ The staged compiler is installed under
`.pycircuit_out/toolchain/install/`. Set `PYC_TOOLCHAIN_ROOT` to that directory
when running end-to-end builds from a source checkout.

## Agentic Circuit and ACIR

ACIR remains an independent, upper-level MLIR dialect. It is not folded into
the PYC dialect and does not replace the Cycle-Aware Signal model:

```text
agentic_circuit frontend -> ACPy 0.3 -> ACIR
|-> ACSim -> gfsim
`-> PYC -> pycc -> pyc6 C++ / Verilog

pycircuit frontend -> Cycle-Aware Signal -> PYC -> pycc -> pyc6 C++ / Verilog
```

The public `agentic_circuit` import and `agentic-circuit` CLI remain distinct
from `pycircuit`. AC symbols are not re-exported from `pycircuit.__init__`.
See the [ACIR architecture overview](docs/acir/index.md) and
[migration record](docs/acir/migration.md).

## First cycle-aware design

```python
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bash flows/scripts/run_sims.sh
```

Run the Agentic Circuit frontend and contract lane:

```bash
PYTHONPATH=components/agentic-circuit/src \
python3 -m unittest discover \
-s components/agentic-circuit/tests \
-p 'test_*.py'
```

System tests require a built toolchain and Verilator:

```bash
Expand All @@ -124,12 +162,16 @@ pytest tests/system -m system
- [IR specification](docs/IR_SPEC.md)
- [pyCircuit 6 decisions](docs/rfcs/pyc6-decisions.md)
- [pyCircuit 6 evolution plan](docs/pyc6-plan.md)
- [ACIR architecture and frontend](docs/acir/index.md)
- [Agentic Circuit migration](docs/acir/migration.md)

## Repository governance

PTO-ISA owns product decisions, releases, package publication, and the default
branch. Linx integration changes should be developed so they can be reviewed
upstream; the LinxISA fork follows the upstream default branch.
PTO-ISA owns product decisions, both Python distributions, releases, package
publication, and the default branch. Linx integration changes should be
developed so they can be reviewed upstream; the LinxISA fork follows the
upstream default branch. The former standalone Agentic Circuit repository is
retired only after both AC and PYC closure gates pass.

- [Contribution workflow](docs/development/contributing-workflow.md)
- [Testing and gates](docs/development/testing-and-gates.md)
Expand All @@ -146,6 +188,7 @@ trace, and gate contracts use `libpyc6_runtime`, `PYC6TRC3`, and
pyCircuit/
├── compiler/frontend/pycircuit/ # Python language frontend
├── compiler/mlir/ # pyc dialect, passes, pycc, and emitters
├── components/agentic-circuit/ # AC frontend, ACIR/ACSim, gfsim, and AC tools
├── runtime/ # C++ simulation and Verilog primitives
├── designs/examples/ # Supported product examples
├── flows/ # Build and validation orchestration
Expand All @@ -155,4 +198,6 @@ pyCircuit/

## License

pyCircuit is licensed under the MIT License. See [LICENSE](LICENSE).
pyCircuit, including the integrated Agentic Circuit sources, is licensed under
the BSD 3-Clause License. See [LICENSE](LICENSE) and the
[relicensing record](docs/legal/AC-RELICENSE-BSD-3-CLAUSE.md).
1 change: 1 addition & 0 deletions components/agentic-circuit/.clang-format
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BasedOnStyle: LLVM
47 changes: 47 additions & 0 deletions components/agentic-circuit/.clang-tidy
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# clang-tidy gate for Agentic Circuit owned sources.
#
# The gate enforces the static analyzer plus high-signal bugprone/performance
# checks that hold across the entire owned tree. Noise-heavy checks whose
# findings are dominated by MLIR/gtest idioms (macro parentheses, optional
# access heuristics, generated enum sizing, gtest static initialization) are
# intentionally out of scope for the CI gate.
Checks: >
-*,
clang-analyzer-*,
bugprone-assert-side-effect,
bugprone-bool-pointer-implicit-conversion,
bugprone-dangling-handle,
bugprone-exception-escape,
bugprone-implicit-widening-of-multiplication-result,
bugprone-inc-dec-in-conditions,
bugprone-inaccurate-erase,
bugprone-infinite-loop,
bugprone-misplaced-operator-in-strlen-in-alloc,
bugprone-misplaced-widening-cast,
bugprone-not-null-terminated-result,
bugprone-optional-value-conversion,
bugprone-posix-return,
bugprone-string-constructor,
bugprone-stringview-nullptr,
bugprone-suspicious-missing-comma,
bugprone-suspicious-realloc-usage,
bugprone-suspicious-string-compare,
bugprone-swapped-arguments,
bugprone-undelegated-constructor,
bugprone-undefined-memory-manipulation,
bugprone-unhandled-self-assignment,
bugprone-use-after-move,
bugprone-virtual-near-miss,
performance-faster-string-find,
performance-implicit-conversion-in-loop,
performance-inefficient-algorithm,
performance-inefficient-string-concatenation,
performance-move-const-arg,
performance-no-automatic-move,
performance-no-int-to-ptr,
performance-trivially-destructible,
performance-type-promotion-in-math-fn,
performance-unnecessary-copy-initialization,
-clang-analyzer-core.StackAddressEscape
WarningsAsErrors: '*'
HeaderFilterRegex: '.*agentic-circuit/(include|lib|tools|unittests)/.*'
15 changes: 15 additions & 0 deletions components/agentic-circuit/.editorconfig
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root = true

[*]
charset = utf-8
end_of_line = lf
insert_final_newline = true
trim_trailing_whitespace = true
indent_style = space
indent_size = 2

[*.py]
indent_size = 4

[Makefile]
indent_style = tab
9 changes: 9 additions & 0 deletions components/agentic-circuit/.gitattributes
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* text=auto eol=lf
*.bat text eol=crlf
*.cmd text eol=crlf
*.png binary
*.jpg binary
*.jpeg binary
*.gif binary
*.pdf binary
references/davincioo-gfsim/upstream/** whitespace=-trailing-space
10 changes: 10 additions & 0 deletions components/agentic-circuit/.github/dependabot.yml
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version: 2
updates:
- package-ecosystem: "github-actions"
directory: "/"
schedule:
interval: "monthly"
- package-ecosystem: "pip"
directory: "/"
schedule:
interval: "monthly"
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