riscv: backport vector extension context save/restore fixes#103
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riscv: backport vector extension context save/restore fixes#103zzSunil wants to merge 572 commits into
zzSunil wants to merge 572 commits into
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开始测试 |
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check patch done. log: https://jenkins.oerv.ac.cn/job/rvck-pipeline/job/check-patch/89/consoleFull |
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Kernel build success! |
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kunit test done. log:https://jenkins.oerv.ac.cn/job/rvck-pipeline/job/kunit-test/96/consoleFull |
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开始测试 |
This patch utilizes Vector to perform copy_to_user/copy_from_user. If Vector is available and the size of copy is large enough for Vector to perform better than scalar, then direct the kernel to do Vector copies for userspace. Though the best programming practice for users is to reduce the copy, this provides a faster variant when copies are inevitable. The optimal size for using Vector, copy_to_user_thres, is only a heuristic for now. We can add DT parsing if people feel the need of customizing it. The exception fixup code of the __asm_vector_usercopy must fallback to the scalar one because accessing user pages might fault, and must be sleepable. Current kernel-mode Vector does not allow tasks to be preemptible, so we must disactivate Vector and perform a scalar fallback in such case. The original implementation of Vector operations comes from https://github.com/sifive/sifive-libc, which we agree to contribute to Linux kernel. Co-developed-by: Jerry Shih <jerry.shih@sifive.com> Signed-off-by: Jerry Shih <jerry.shih@sifive.com> Co-developed-by: Nick Knight <nick.knight@sifive.com> Signed-off-by: Nick Knight <nick.knight@sifive.com> Suggested-by: Guo Ren <guoren@kernel.org> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20240115055929.4736-6-andy.chiu@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
SR_SD summarizes the dirty status of FS/VS/XS. However, the current code structure does not fully utilize it because each extension specific code is divided into an individual segment. So remove the SR_SD check for now. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Song Shuai <songshuaishuai@tinylab.org> Reviewed-by: Guo Ren <guoren@kernel.org> Tested-by: Björn Töpel <bjorn@rivosinc.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20240115055929.4736-7-andy.chiu@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
…ore}()
riscv_v_vstate_{save,restore}() can operate only on the knowlege of
struct __riscv_v_ext_state, and struct pt_regs. Let the caller decides
which should be passed into the function. Meanwhile, the kernel-mode
Vector is going to introduce another vstate, so this also makes functions
potentially able to be reused.
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240115055929.4736-8-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
riscv_v_ctrl_set() should only touch bits within PR_RISCV_V_VSTATE_CTRL_MASK. So, use the mask when we really set task's vstate_ctrl. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20240115055929.4736-9-andy.chiu@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
The allocation size of thread.vstate.datap is always riscv_v_vsize. So it is possbile to use kmem_cache_* to manage the allocation. This gives users more information regarding allocation of vector context via /proc/slabinfo. And it potentially reduces the latency of the first-use trap because of the allocation caches. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20240115055929.4736-10-andy.chiu@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Add kernel_vstate to keep track of kernel-mode Vector registers when trap introduced context switch happens. Also, provide riscv_v_flags to let context save/restore routine track context status. Context tracking happens whenever the core starts its in-kernel Vector executions. An active (dirty) kernel task's V contexts will be saved to memory whenever a trap-introduced context switch happens. Or, when a softirq, which happens to nest on top of it, uses Vector. Context retoring happens when the execution transfer back to the original Kernel context where it first enable preempt_v. Also, provide a config CONFIG_RISCV_ISA_V_PREEMPTIVE to give users an option to disable preemptible kernel-mode Vector at build time. Users with constraint memory may want to disable this config as preemptible kernel-mode Vector needs extra space for tracking of per thread's kernel-mode V context. Or, users might as well want to disable it if all kernel-mode Vector code is time sensitive and cannot tolerate context switch overhead. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20240115055929.4736-11-andy.chiu@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Implement CONFIG_SHADOW_CALL_STACK for RISC-V. When enabled, the compiler injects instructions to all non-leaf C functions to store the return address to the shadow stack and unconditionally load it again before returning, which makes it harder to corrupt the return address through a stack overflow, for example. The active shadow call stack pointer is stored in the gp register, which makes SCS incompatible with gp relaxation. Use --no-relax-gp to ensure gp relaxation is disabled and disable global pointer loading. Add SCS pointers to struct thread_info, implement SCS initialization, and task switching Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Tested-by: Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20230927224757.1154247-12-samitolvanen@google.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Author
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Sync OLK-6.6 updates. |
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开始测试 |
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check patch done. log: https://jenkins.oerv.ac.cn/job/rvck-pipeline/job/check-patch/112/consoleFull |
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check patch done. log: https://jenkins.oerv.ac.cn/job/rvck-pipeline/job/check-patch/113/consoleFull |
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Kernel build success! |
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kunit test done. log:https://jenkins.oerv.ac.cn/job/rvck-pipeline/job/kunit-test/116/consoleFull |
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Kernel build success! |
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kunit test done. log:https://jenkins.oerv.ac.cn/job/rvck-pipeline/job/kunit-test/117/consoleFull |
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Lava check done! result url: https://lava.oerv.ac.cn/scheduler/job/433 |
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Lava check done! result url: https://lava.oerv.ac.cn/scheduler/job/434 |
Collaborator
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/check 开始测试 log: https://github.com/RVCK-Project/rvck-olk/actions/runs/17713630143 参数解析结果
测试完成 详细结果:RVCK result
Kunit Test Result[16:21:42] Testing complete. Ran 454 tests: passed: 442, skipped: 12 Kernel Build ResultKernel build failed. c178b8e1a3f65036b60094cd7939e01c /srv/guix_result/783f781ffd8f05511803760a62ca5bd9b0c6abaf/Image Check Patch Result
测试完成 详细结果:RVCK result
Kunit Test Result[16:21:42] Testing complete. Ran 454 tests: passed: 442, skipped: 12 Kernel Build ResultKernel build failed. c178b8e1a3f65036b60094cd7939e01c /srv/guix_result/783f781ffd8f05511803760a62ca5bd9b0c6abaf/Image Check Patch Result
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Collaborator
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/check 开始测试 log: https://github.com/RVCK-Project/rvck-olk/actions/runs/17722697184 参数解析结果
测试完成 详细结果:RVCK result
Kunit Test Result[05:13:56] Testing complete. Ran 454 tests: passed: 442, skipped: 12 Kernel Build ResultKernel build succeeded: RVCK-Project/rvck-olk/103_3290506391/ 35ce9ebc7a1fe4de7dfe58d413f46382 /srv/guix_result/783f781ffd8f05511803760a62ca5bd9b0c6abaf/Image LAVA Checkargs:
result:Lava check done! lava log: https://lava.oerv.ac.cn/scheduler/job/745 lava result count: [fail]: 18, [pass]: 1588, [skip]: 293 Check Patch Result
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Resolves #104