Skip to content

Rename arbiter module to verilog_axis_arbiter #21

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open

Rename arbiter module to verilog_axis_arbiter #21

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion rtl/arbiter.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ THE SOFTWARE.
/*
* Arbiter module
*/
module arbiter #
module verilog_axis_arbiter #
(
parameter PORTS = 4,
// select round robin arbitration
Expand Down
2 changes: 1 addition & 1 deletion rtl/axis_arb_mux.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -151,7 +151,7 @@ wire [DEST_WIDTH-1:0] current_s_tdest = s_axis_tdest_reg[grant_encoded*DEST_WID
wire [USER_WIDTH-1:0] current_s_tuser = s_axis_tuser_reg[grant_encoded*USER_WIDTH +: USER_WIDTH];

// arbiter instance
arbiter #(
verilog_axis_arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
Expand Down
8 changes: 4 additions & 4 deletions rtl/axis_ram_switch.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -284,7 +284,7 @@ generate

if (S_COUNT > 1) begin

arbiter #(
verilog_axis_arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(1),
.ARB_BLOCK(0),
Expand Down Expand Up @@ -320,7 +320,7 @@ generate

if (M_COUNT > 1) begin

arbiter #(
verilog_axis_arbiter #(
.PORTS(M_COUNT),
.ARB_TYPE_ROUND_ROBIN(1),
.ARB_BLOCK(0),
Expand Down Expand Up @@ -504,7 +504,7 @@ generate
wire grant_valid;
wire [CL_M_COUNT-1:0] grant_encoded;

arbiter #(
verilog_axis_arbiter #(
.PORTS(M_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
Expand Down Expand Up @@ -824,7 +824,7 @@ generate
wire grant_valid;
wire [CL_S_COUNT-1:0] grant_encoded;

arbiter #(
verilog_axis_arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
Expand Down
2 changes: 1 addition & 1 deletion rtl/axis_switch.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -318,7 +318,7 @@ generate
wire grant_valid;
wire [CL_S_COUNT-1:0] grant_encoded;

arbiter #(
verilog_axis_arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
Expand Down
2 changes: 1 addition & 1 deletion tb/test_arbiter.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -71,7 +71,7 @@ initial begin
$dumpvars(0, test_arbiter);
end

arbiter #(
verilog_axis_arbiter #(
.PORTS(PORTS),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(ARB_BLOCK),
Expand Down
2 changes: 1 addition & 1 deletion tb/test_arbiter_rr.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -71,7 +71,7 @@ initial begin
$dumpvars(0, test_arbiter_rr);
end

arbiter #(
verilog_axis_arbiter #(
.PORTS(PORTS),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(ARB_BLOCK),
Expand Down