cn0577_adaq2387x: Add testbench

[StancaPop]

PR Description

Add testbench support for cn0577 & adaq2387x.

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• New test (change that adds new test program and/or testbench)
• Breaking change (has dependencies in other repositories/testbenches)
• Documentation (change that adds or modifies documentation)

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have ran all testbenches affected by this PR
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Errors on compilation/elaboration/simulation
• I have set the verbosity level to none for the test program

[StancaPop]

To be tested with analogdevicesinc/hdl#1870

[StancaPop]

To be used with the HDL main branch.

[StancaPop]

Converting the testbench to draft since the cn0577 HDL reference design will be updated here: analogdevicesinc/hdl#1919

This will cause the testbench to fail because of the following modification:

• ADC_RES parameter has been removed; the cn0577 design will support only the LTC2387-18 variant

Solution:

• This testbench can be renamed and repurposed for the adaq2387x family, that was separated from the cn0577 (both being built around axi_ltc2387) and supports both resolutions. The HDL project is still under development.

[StancaPop]

Since the cn0577 & adaq2387x projects have been separated in HDL, repurposed this testbench to support both projects.
To be tested with: https://github.com/analogdevicesinc/hdl/tree/add_adaq2387x_s

[IstvanZsSzekely]

Not used in the system_tb, it has its own logic to create the dco_p and dco_n signals.

[IstvanZsSzekely]

Please review the input and output signals and update the lists in the test_program, as well as in the system_tb.
Note: system_tb was updated, dco_p and dco_n signals are generated inside the test_program.

[IstvanZsSzekely]

CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/axi_ltc2387/delay_clk
Related: WARNING: [BD 41-597] NET <sys_200m_clk> has no source

[StancaPop]

CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /axi_ltc2387/delay_clk Related: WARNING: [BD 41-597] NET <sys_200m_clk> has no source

Resolved in 176ab82
Disconnected the delay_clk from sys_200m_clk and connected it to sys_dma_clk.

[IstvanZsSzekely]

Please review the input and output signals and update the lists in the test_program, as well as in the system_tb.
Note: system_tb was updated, dco_p and dco_n signals are generated inside the test_program.

[IstvanZsSzekely]

See previous comment on dco_p/dco_n.

[IstvanZsSzekely]

Since the forever loop is running endlessly, the simulation never passes time 0. Please add a time consuming statement that prevents the hang.
@(posedge clk_gate, negedge clk_gate); seems to be working if added before the conditional statement, but please verify that the testbench is still working as expected.