UDB Routing Configuration

##PLD Port Interface (PI) Tiles

B[1..3]_P[0..7]_ROUTE_PLD[0..1]IN[0..2]

There are three 4 bit fields to for each PLD. These bits connect the Input Terms to the routing channel. 4*3=12, one bit for each of the 12 Input Terms. The most significant 4 bits of each register are for the bottom UDB of the Pair. The least significant 4 bits are for the top UDB of the Pair. The nybles are flipped for the top UDB's PLD.

###Examples

Connect IT1 and IT4 of the bottom UDB (U0) of Pair 4 in Bank 1:

B1_P4_ROUTE_PLD0IN0 <- 0x20 # IT1
B1_P4_ROUTE_PLD0IN1 <- 0x10 # IT4
B1_P4_ROUTE_PLD0IN2 <- 0x00

Connect IT1 and IT4 of the top UDB (U1) of Pair 4 in Bank 1:

B1_P4_ROUTE_PLD0IN0 <- 0x04 # IT1
B1_P4_ROUTE_PLD0IN1 <- 0x08 # IT4
B1_P4_ROUTE_PLD0IN2 <- 0x00