Digital System Routing
The DSI blocks exist in two rows either above or below the 4x4 UDB Bank 0 and the 4x2 UDB Bank 1. UDB pairs are directly above or below their corresponding DSI blocks in the same order.
There is connectivity across DSI's over or under different UDB Banks but not across internal UDB array routing of different UDB Banks. If you want to get two inputs from PRT1, implement an XOR gate in B1_P4, and then route the output to PRT2, you will need to route your output of B1_P4 back into the DSI to get to DSI5 and PRT2.
An output pin can be configured to be driven by 4 of the 8 available DSIs using PRTx_OUT_SEL0 and PRTx_OUT_SEL1 (Bank 0 has 4 top DSIs and 4 bottom DSIs).
Input ports are connected directly to a fixed DSI. Each port is associated with a single DSI block. The registers of the DSI PI Tiles:
DSI[0..15]_DSIINP0
DSI[0..15]_DSIINP1
DSI[0..15]_DSIINP2
DSI[0..15]_DSIINP3
DSI[0..15]_DSIINP4
DSI[0..15]_DSIINP5
work like the PLD PI tiles. Each bit represents an input pin of the DSI's corresponding port for top row DSIs these bits are spread out over the bottom nybles of the aforementioned registers (but flipped). The high nyble is not implemented in top DSI blocks. For the bottom DSI blocks, same thing except the high nyble is used (not flipped) and the low nyble is not implemented.
B[1..3]_P[0..7]_ROUTE_PLD[0..1]IN[0..2]
There are three 4 bit fields to for each PLD. These bits connect the Input Terms to the routing channel. 4*3=12, one bit for each of the 12 Input Terms. The most significant 4 bits of each register are for the bottom UDB of the Pair. The least significant 4 bits are for the top UDB of the Pair. The nybles are flipped for the top UDB's PLD.
Connect IT1 and IT4 of the bottom UDB of Pair 4 in Bank 1:
B1_P4_ROUTE_PLD0IN0 <- 0x20 # IT1
B1_P4_ROUTE_PLD0IN1 <- 0x10 # IT4
B1_P4_ROUTE_PLD0IN2 <- 0x00
Connect IT1 and IT4 of the top UDB (U1) of Pair 4 in Bank 1:
B1_P4_ROUTE_PLD0IN0 <- 0x04 # IT1
B1_P4_ROUTE_PLD0IN1 <- 0x08 # IT4
B1_P4_ROUTE_PLD0IN2 <- 0x00
In B1_P4, U0 is the bottom UDB and U1 is the top UDB. Use the pattern in the diagram above to determine which of U0 and U1 is the upper UDB and which is the lower UDB.
