Add SIML FEPGate (one-bit surprise gating) to V-JEPA 2 planning loop

[lesreaper]

Motivation
Short-horizon latent planning can waste samples in spurious minima. We add a one-bit surprise gate (FEPGate) that prunes high-surprise elites during CEM/MPC, improving both accuracy and efficiency—no model retraining.

Paper Link

What’s in this PR
Optional SIML sidecar integration (surprise, step CLI) via .npy + JSON IPC
Elite-set gating hook in the CEM loop (hard/soft)
τ-calibration script (obs-driven 5–10th percentile)
Repro harness for OFF vs FEP comparisons (100 eps reaching)
Plots (violin, latency, energy) and hero schematic

Key results (frozen V-JEPA 2, same budget)
Final error 0.193 m → 0.109 m
Monotonicity 0.12 → 0.43
Latency 2.28 s → 1.13 s
Energy/episode 0.058 Wh → 0.029 Wh
EDP ~4× lower

How to run

From /src
# 1) Calibrate τ once per scene
python siml/scripts/calibrate_tau.py --sigma 1e-3 --p 0.05

# 2) Eval baseline and FEP
python siml/scripts/power_wrap.py --out siml/results/reaching_off/power.json --   python -m siml.evals.reach_eval     --config siml/configs/eval/siml_reaching.yaml     --out_dir siml/results/reaching_off     --only off

python siml/scripts/power_wrap.py --out siml/results/reaching_fep/power.json --   python -m siml.evals.reach_eval     --confi
g siml/configs/eval/siml_reaching.yaml     --out_dir siml/results/reaching_fep    
--only fepgate

# 3) Plot
python siml/scripts/summarize_reaching.py

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