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The purpose of the PR is solely to review the patch set that will be submitted to upstream.

This commit introduces a new -mtune=rmx100 tuning option together with
relevant scheduler definitions. Instruction latencies and costs are based on
the "RMX-100 Technical Reference Manual" document (revision 0.4, 13
September 2023) and are subject to change.

The changes have been verified by running the Dhrystone and Coremark benchmarks
and observing expected (small) improvements compared to the -mtune=generic
results.

Signed-off-by: Artemiy Volkov <[email protected]>
This commit adds the new arcv-mpy-option compilation parameter with the valid
(string) values of 1c, 2c, and 10c.  This corresponds to different versions of
the MPY/DIV unit of the RMX100 core, each of which has different latencies for
imul/idiv instructions.

Internally, this option is propagated to the pipeline description information
in rmx100.md with the use of new helper functions defined in riscv.cc.

Signed-off-by: Artemiy Volkov <[email protected]>
Since it is critical to scheduling for the RMX-100 core, allow setting
load latency via a newly create target-specific arcv-ld-cycles
parameter. The worst case latency is 3, and so is the parameter's
default value.

Signed-off-by: Artemiy Volkov <[email protected]>
@MichielDerhaeg MichielDerhaeg force-pushed the michiel/upstream_rmx100 branch from 0efc8b2 to 2fa36eb Compare October 1, 2025 11:42

-param=arcv-mpy-option=
Target RejectNegative Joined Enum(arcv_mpy_option) Var(arcv_mpy_option) Init(ARCV_MPY_OPTION_2C)
The type of MPY unit used by the RMX-100 core (to be used in combination with -mtune=rmx100) (default: 2c).
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FIXME

}

/* Implement one boolean function for each of the values of the
arcv_mpy_option enum, for the needs of rhx100.md. */
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FIXME

(define_automaton "arcv_rmx100")

(define_cpu_unit "arcv_rmx100_ALU" "arcv_rmx100")
;(define_cpu_unit "arcv_rmx100_CSR" "arcv_rmx100")
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FIXME

Comment on lines +80 to +82
;;(define_insn_reservation "core" 1
;; (eq_attr "type" "block, brk, dmb, flag, lr, sr, sync")
;; "arcv_rmx100_ALU0 + arcv_rmx100_ALU1 + arcv_rmx100_DMP + arcv_rmx100_MPY + arcv_rmx100_MPY64 + arcv_rmx100_DIV")
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FIXME

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2 participants