arc: emit clobber of CC for -mcpu=em x >> 31 #186
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Address the issue explained here: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120375 If the target has no barrel shifter, clobber is now emitted in a parallel RTL expression. <insn>si3_loop matches the parallel expression and emits the necessary expressions that may or may not clobber the CC. This happens in split1, before registers are assigned and dead stores are removed. If the clobber was unnecessary, its consequences will be removed by those steps. <insn>si3_cnt1_clobber is placed below all the specific si3_cnt1 patterns. It matches the <insn>si3_loop pattern in the case operand2 has become const_int 1, and remove the clobber so the specific si3_cnt1 patterns can be matched. If <insn>si3_cnt1_clobber is placed above these patterns, some si3_cnt would try to emit extra clobbers to match it instead of their more specific pattern that match exactly. This would cause clobbers of hard registers, causing failure.
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Fixed solution that was merged in #181 but was reverted because it caused issues. It has been built and tested on the jenkins without issues.