Add more fakes

.github/workflows/rust.yml

@@ -21,7 +21,7 @@ jobs:
           - armv7a-none-eabi
     steps:
       - uses: actions/checkout@v4
-      - name: Install aarch64 toolchain
+      - name: Install ${{ matrix.target }} toolchain
         uses: actions-rs/toolchain@v1
         with:
           toolchain: stable
@@ -35,11 +35,18 @@ jobs:
           args: --target ${{ matrix.target }}
 
   test:
+    permissions:
+      checks: write
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v4
       - name: Test on host
-        run: cargo test --target=x86_64-unknown-linux-gnu --lib
+        run: cargo test --features=fakes
+      - name: Run clippy
+        uses: actions-rs/clippy-check@v1
+        with:
+          token: ${{ secrets.GITHUB_TOKEN }}
+          args: --features=fakes
 
   format:
     runs-on: ubuntu-latest

CHANGELOG.md

@@ -1,5 +1,15 @@
 # Changelog
 
+## Unreleased
+
+### Bugfixes
+
+- Fixed example in crate documentation.
+
+### Improvements
+
+- Added fakes for `irq_disable`, `irq_enable` and `wfi`.
+
 ## 0.5.0
 
 ### Breaking changes

src/lib.rs

@@ -11,34 +11,39 @@
 //!
 //! Using a GICv3 on a single-core aarch64 system:
 //!
-//! ```
+//! ```no_run
 //! use arm_gic::{
-//!     gicv3::{GicV3, SgiTarget},
-//!     irq_enable, IntId,
+//!     IntId,
+//!     gicv3::{
+//!         GicV3, SgiTarget, SgiTargetGroup,
+//!         registers::{Gicd, GicrSgi},
+//!     },
+//!     irq_enable,
 //! };
 //!
 //! // Base addresses of the GICv3 distributor and redistributor.
-//! const GICD_BASE_ADDRESS: *mut u64 = 0x800_0000 as _;
-//! const GICR_BASE_ADDRESS: *mut u64 = 0x80A_0000 as _;
+//! const GICD_BASE_ADDRESS: *mut Gicd = 0x800_0000 as _;
+//! const GICR_BASE_ADDRESS: *mut GicrSgi = 0x80A_0000 as _;
 //!
 //! // Initialise the GIC.
-//! let mut gic = unsafe { GicV3::new(GICD_BASE_ADDRESS, GICR_BASE_ADDRESS, 1, 0x20000) };
+//! let mut gic = unsafe { GicV3::new(GICD_BASE_ADDRESS, GICR_BASE_ADDRESS, 1, false) };
 //! gic.setup(0);
 //!
 //! // Configure an SGI and then send it to ourself.
 //! let sgi_intid = IntId::sgi(3);
-//! SingleCoreGicV3::set_priority_mask(0xff);
+//! GicV3::set_priority_mask(0xff);
 //! gic.set_interrupt_priority(sgi_intid, Some(0), 0x80);
 //! gic.enable_interrupt(sgi_intid, Some(0), true);
 //! irq_enable();
-//! SingleCoreGicV3::send_sgi(
+//! GicV3::send_sgi(
 //!     sgi_intid,
 //!     SgiTarget::List {
 //!         affinity3: 0,
 //!         affinity2: 0,
 //!         affinity1: 0,
 //!         target_list: 0b1,
 //!     },
+//!     SgiTargetGroup::CurrentGroup1,
 //! );
 //! ```
 
@@ -53,8 +58,10 @@ mod sysreg;
 
 #[cfg(feature = "fakes")]
 pub use sysreg::fake as sysreg_fake;
+#[cfg(feature = "fakes")]
+pub use sysreg::fake::{irq_disable, irq_enable, wfi};
 
-#[cfg(target_arch = "aarch64")]
+#[cfg(all(target_arch = "aarch64", not(feature = "fakes")))]
 use core::arch::asm;
 use core::fmt::{Debug, Formatter, Result};
 
@@ -236,7 +243,7 @@ impl From<IntId> for u32 {
 }
 
 /// Disables debug, SError, IRQ and FIQ exceptions.
-#[cfg(target_arch = "aarch64")]
+#[cfg(all(target_arch = "aarch64", not(feature = "fakes")))]
 pub fn irq_disable() {
     // SAFETY: Writing to this system register doesn't access memory in any way.
     unsafe {
@@ -245,7 +252,7 @@ pub fn irq_disable() {
 }
 
 /// Enables debug, SError, IRQ and FIQ exceptions.
-#[cfg(target_arch = "aarch64")]
+#[cfg(all(target_arch = "aarch64", not(feature = "fakes")))]
 pub fn irq_enable() {
     // SAFETY: Writing to this system register doesn't access memory in any way.
     unsafe {
@@ -254,7 +261,7 @@ pub fn irq_enable() {
 }
 
 /// Waits for an interrupt.
-#[cfg(target_arch = "aarch64")]
+#[cfg(all(target_arch = "aarch64", not(feature = "fakes")))]
 pub fn wfi() {
     // SAFETY: This doesn't access memory in any way.
     unsafe {

src/sysreg/fake.rs

@@ -26,6 +26,7 @@ pub struct SystemRegisters {
     pub icc_sgi0r_el1: u64,
     pub icc_sgi1r_el1: u64,
     pub icc_sre_el1: u32,
+    pub daif: u64,
 }
 
 impl SystemRegisters {
@@ -45,6 +46,7 @@ impl SystemRegisters {
             icc_sgi0r_el1: 0,
             icc_sgi1r_el1: 0,
             icc_sre_el1: 0,
+            daif: 0,
         }
     }
 }
@@ -77,3 +79,18 @@ macro_rules! write_sysreg64 {
         }
     };
 }
+
+/// Disables debug, SError, IRQ and FIQ exceptions.
+pub fn irq_disable() {
+    SYSREGS.lock().unwrap().daif = 0b11_1100_0000;
+}
+
+/// Enables debug, SError, IRQ and FIQ exceptions.
+pub fn irq_enable() {
+    SYSREGS.lock().unwrap().daif = 0;
+}
+
+/// Waits for an interrupt.
+pub fn wfi() {
+    // No-op, just return immediately.
+}