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[AMDGPU] Allow unaligned VGPR for ds_read_b96_tr_b6 #125169

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Merged
merged 1 commit into from
Jan 31, 2025
Merged

[AMDGPU] Allow unaligned VGPR for ds_read_b96_tr_b6 #125169

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5 changes: 4 additions & 1 deletion llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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Expand Up @@ -4853,7 +4853,10 @@ bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {

bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {
auto FB = getFeatureBits();
if (!FB[AMDGPU::FeatureGFX90AInsts])
unsigned Opc = Inst.getOpcode();
// DS_READ_B96_TR_B6 is the only DS instruction in GFX950, that allows
// unaligned VGPR. All others only allow even aligned VGPRs.
if (!(FB[AMDGPU::FeatureGFX90AInsts]) || Opc == AMDGPU::DS_READ_B96_TR_B6_vi)
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Extra parentheses. Also we probably should not directly special case the opcode here. This should come from the register class constraint of the operand

return true;

const MCRegisterInfo *MRI = getMRI();
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4 changes: 0 additions & 4 deletions llvm/test/MC/AMDGPU/gfx950-unsupported.s
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Expand Up @@ -239,10 +239,6 @@ ds_read_b64_tr_b16 v[2:3], v2 offset:-64
//===----------------------------------------------------------------------===//
// ds_read_b96_tr_b6
//===----------------------------------------------------------------------===//
ds_read_b96_tr_b6 v[1:3], v0
// ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU

ds_read_b96_tr_b6 v1, v0
// ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
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8 changes: 8 additions & 0 deletions llvm/test/MC/AMDGPU/gfx950_asm_read_tr.s
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Expand Up @@ -32,3 +32,11 @@ ds_read_b96_tr_b6 v[0:2], v0
ds_read_b96_tr_b6 v[2:4], v2 offset:64
// GFX940-ERR: [[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
// GFX950: encoding: [0x40,0x00,0xc2,0xd9,0x02,0x00,0x00,0x02]

ds_read_b96_tr_b6 v[1:3], v0
// GFX940-ERR: [[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
// GFX950: encoding: [0x00,0x00,0xc2,0xd9,0x00,0x00,0x00,0x01]

ds_read_b96_tr_b6 v[1:3], v2 offset:64
// GFX940-ERR: [[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
// GFX950: encoding: [0x40,0x00,0xc2,0xd9,0x02,0x00,0x00,0x01]
6 changes: 6 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_ds_read_tr.txt
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Expand Up @@ -35,3 +35,9 @@

# GFX950: ds_read_b96_tr_b6 v[2:4], v2 offset:64 ; encoding: [0x40,0x00,0xc2,0xd9,0x02,0x00,0x00,0x02]
0x40,0x00,0xc2,0xd9,0x02,0x00,0x00,0x02

# GFX950: ds_read_b96_tr_b6 v[1:3], v0 ; encoding: [0x00,0x00,0xc2,0xd9,0x00,0x00,0x00,0x01]
0x00,0x00,0xc2,0xd9,0x00,0x00,0x00,0x01

# GFX950: ds_read_b96_tr_b6 v[1:3], v2 offset:64 ; encoding: [0x40,0x00,0xc2,0xd9,0x02,0x00,0x00,0x01]
0x40,0x00,0xc2,0xd9,0x02,0x00,0x00,0x01