Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" #126684
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@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-backend-powerpc Author: Akshat Oke (optimisan) Changes
Now the Impl class is a member of the legacy and new passes so that it is not reconstructed on every pass run. Patch is 65.59 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/126684.diff 56 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index 4762494e6ccb77d..42912cc9cb539aa 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -98,6 +98,10 @@
#include <vector>
namespace llvm {
+namespace impl_detail {
+class MachineSchedulerImpl;
+class PostMachineSchedulerImpl;
+} // namespace impl_detail
namespace MISched {
enum Direction {
@@ -1385,6 +1389,30 @@ std::unique_ptr<ScheduleDAGMutation>
createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI);
+class MachineSchedulerPass : public PassInfoMixin<MachineSchedulerPass> {
+ std::unique_ptr<impl_detail::MachineSchedulerImpl> Impl;
+ const TargetMachine *TM;
+
+public:
+ MachineSchedulerPass(const TargetMachine *TM);
+ MachineSchedulerPass(MachineSchedulerPass &&Other);
+ ~MachineSchedulerPass();
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
+class PostMachineSchedulerPass
+ : public PassInfoMixin<PostMachineSchedulerPass> {
+ std::unique_ptr<impl_detail::PostMachineSchedulerImpl> Impl;
+ const TargetMachine *TM;
+
+public:
+ PostMachineSchedulerPass(const TargetMachine *TM);
+ PostMachineSchedulerPass(PostMachineSchedulerPass &&Other);
+ ~PostMachineSchedulerPass();
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
} // end namespace llvm
#endif // LLVM_CODEGEN_MACHINESCHEDULER_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 6d74d7f24bf9a82..b8df4d1ecab1d0f 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -209,7 +209,7 @@ void initializeMachinePipelinerPass(PassRegistry &);
void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializeMachineRegionInfoPassPass(PassRegistry &);
void initializeMachineSanitizerBinaryMetadataPass(PassRegistry &);
-void initializeMachineSchedulerPass(PassRegistry &);
+void initializeMachineSchedulerLegacyPass(PassRegistry &);
void initializeMachineSinkingPass(PassRegistry &);
void initializeMachineTraceMetricsWrapperPassPass(PassRegistry &);
void initializeMachineUniformityInfoPrinterPassPass(PassRegistry &);
@@ -238,7 +238,7 @@ void initializePostDomPrinterWrapperPassPass(PassRegistry &);
void initializePostDomViewerWrapperPassPass(PassRegistry &);
void initializePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializePostInlineEntryExitInstrumenterPass(PassRegistry &);
-void initializePostMachineSchedulerPass(PassRegistry &);
+void initializePostMachineSchedulerLegacyPass(PassRegistry &);
void initializePostRAHazardRecognizerPass(PassRegistry &);
void initializePostRAMachineSinkingPass(PassRegistry &);
void initializePostRASchedulerLegacyPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 7f91dd7ebf49de9..1458318ff021a98 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -50,6 +50,7 @@
#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MachineVerifier.h"
#include "llvm/CodeGen/OptimizePHIs.h"
#include "llvm/CodeGen/PHIElimination.h"
@@ -960,7 +961,7 @@ Error CodeGenPassBuilder<Derived, TargetMachineT>::addMachinePasses(
if (getOptLevel() != CodeGenOptLevel::None &&
!TM.targetSchedulesPostRAScheduling()) {
if (Opt.MISchedPostRA)
- addPass(PostMachineSchedulerPass());
+ addPass(PostMachineSchedulerPass(&TM));
else
addPass(PostRASchedulerPass(&TM));
}
@@ -1144,7 +1145,7 @@ void CodeGenPassBuilder<Derived, TargetMachineT>::addOptimizedRegAlloc(
addPass(RenameIndependentSubregsPass());
// PreRA instruction scheduling.
- addPass(MachineSchedulerPass());
+ addPass(MachineSchedulerPass(&TM));
if (derived().addRegAssignmentOptimized(addPass)) {
// Allow targets to expand pseudo instructions depending on the choice of
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 9f9922dfa5673c7..075ebcb82955329 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -142,12 +142,14 @@ MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass())
MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass())
MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass())
MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass())
+MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass(TM))
MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass())
MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass())
MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass())
MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass())
MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass())
MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass(TM))
+MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass(TM))
MACHINE_FUNCTION_PASS("print", PrintMIRPass())
MACHINE_FUNCTION_PASS("print<livedebugvars>", LiveDebugVariablesPrinterPass(errs()))
MACHINE_FUNCTION_PASS("print<live-intervals>", LiveIntervalsPrinterPass(errs()))
@@ -243,13 +245,11 @@ DUMMY_MACHINE_FUNCTION_PASS("static-data-splitter", StaticDataSplitter)
DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata)
-DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass)
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass)
-DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass)
DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles", MachineCycleInfoPrinterPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index d69a24f00871eac..35df2a479a545e7 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -94,7 +94,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeModuloScheduleTestPass(Registry);
initializeMachinePostDominatorTreeWrapperPassPass(Registry);
initializeMachineRegionInfoPassPass(Registry);
- initializeMachineSchedulerPass(Registry);
+ initializeMachineSchedulerLegacyPass(Registry);
initializeMachineSinkingPass(Registry);
initializeMachineUniformityAnalysisPassPass(Registry);
initializeMachineUniformityInfoPrinterPassPass(Registry);
@@ -105,7 +105,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePHIEliminationPass(Registry);
initializePatchableFunctionPass(Registry);
initializePeepholeOptimizerLegacyPass(Registry);
- initializePostMachineSchedulerPass(Registry);
+ initializePostMachineSchedulerLegacyPass(Registry);
initializePostRAHazardRecognizerPass(Registry);
initializePostRAMachineSinkingPass(Registry);
initializePostRASchedulerLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 3f72e8486c06ef8..1be7a33720dbfd5 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -214,69 +214,119 @@ MachineSchedContext::~MachineSchedContext() {
delete RegClassInfo;
}
-namespace {
-
-/// Base class for a machine scheduler class that can run at any point.
-class MachineSchedulerBase : public MachineSchedContext,
- public MachineFunctionPass {
-public:
- MachineSchedulerBase(char &ID) : MachineFunctionPass(ID) {}
+namespace llvm {
+namespace impl_detail {
+/// Base class for the machine scheduler classes.
+class MachineSchedulerBase : public MachineSchedContext {
protected:
void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags);
};
-/// MachineScheduler runs after coalescing and before register allocation.
-class MachineScheduler : public MachineSchedulerBase {
-public:
- MachineScheduler();
+/// Impl class for MachineScheduler.
+class MachineSchedulerImpl : public MachineSchedulerBase {
+ // These are only for using MF.verify()
+ // remove when verify supports passing in all analyses
+ MachineFunctionPass *P = nullptr;
+ MachineFunctionAnalysisManager *MFAM = nullptr;
- void getAnalysisUsage(AnalysisUsage &AU) const override;
+public:
+ struct RequiredAnalyses {
+ MachineLoopInfo &MLI;
+ MachineDominatorTree &MDT;
+ AAResults &AA;
+ LiveIntervals &LIS;
+ };
- bool runOnMachineFunction(MachineFunction&) override;
+ MachineSchedulerImpl() {}
+ // Migration only
+ void setLegacyPass(MachineFunctionPass *P) { this->P = P; }
+ void setMFAM(MachineFunctionAnalysisManager *MFAM) { this->MFAM = MFAM; }
- static char ID; // Class identification, replacement for typeinfo
+ bool run(MachineFunction &MF, const TargetMachine &TM,
+ const RequiredAnalyses &Analyses);
protected:
ScheduleDAGInstrs *createMachineScheduler();
};
-/// PostMachineScheduler runs after shortly before code emission.
-class PostMachineScheduler : public MachineSchedulerBase {
+/// Impl class for PostMachineScheduler.
+class PostMachineSchedulerImpl : public MachineSchedulerBase {
+ // These are only for using MF.verify()
+ // remove when verify supports passing in all analyses
+ MachineFunctionPass *P = nullptr;
+ MachineFunctionAnalysisManager *MFAM = nullptr;
+
public:
- PostMachineScheduler();
+ struct RequiredAnalyses {
+ MachineLoopInfo &MLI;
+ AAResults &AA;
+ };
+ PostMachineSchedulerImpl() {}
+ // Migration only
+ void setLegacyPass(MachineFunctionPass *P) { this->P = P; }
+ void setMFAM(MachineFunctionAnalysisManager *MFAM) { this->MFAM = MFAM; }
- void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool run(MachineFunction &Func, const TargetMachine &TM,
+ const RequiredAnalyses &Analyses);
+
+protected:
+ ScheduleDAGInstrs *createPostMachineScheduler();
+};
+} // namespace impl_detail
+} // namespace llvm
+
+using impl_detail::MachineSchedulerBase;
+using impl_detail::MachineSchedulerImpl;
+using impl_detail::PostMachineSchedulerImpl;
+
+namespace {
+/// MachineScheduler runs after coalescing and before register allocation.
+class MachineSchedulerLegacy : public MachineFunctionPass {
+ MachineSchedulerImpl Impl;
+
+public:
+ MachineSchedulerLegacy();
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
bool runOnMachineFunction(MachineFunction&) override;
static char ID; // Class identification, replacement for typeinfo
+};
-protected:
- ScheduleDAGInstrs *createPostMachineScheduler();
+/// PostMachineScheduler runs after shortly before code emission.
+class PostMachineSchedulerLegacy : public MachineFunctionPass {
+ PostMachineSchedulerImpl Impl;
+
+public:
+ PostMachineSchedulerLegacy();
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool runOnMachineFunction(MachineFunction &) override;
+
+ static char ID; // Class identification, replacement for typeinfo
};
} // end anonymous namespace
-char MachineScheduler::ID = 0;
+char MachineSchedulerLegacy::ID = 0;
-char &llvm::MachineSchedulerID = MachineScheduler::ID;
+char &llvm::MachineSchedulerID = MachineSchedulerLegacy::ID;
-INITIALIZE_PASS_BEGIN(MachineScheduler, DEBUG_TYPE,
+INITIALIZE_PASS_BEGIN(MachineSchedulerLegacy, DEBUG_TYPE,
"Machine Instruction Scheduler", false, false)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
-INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE,
+INITIALIZE_PASS_END(MachineSchedulerLegacy, DEBUG_TYPE,
"Machine Instruction Scheduler", false, false)
-MachineScheduler::MachineScheduler() : MachineSchedulerBase(ID) {
- initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
+MachineSchedulerLegacy::MachineSchedulerLegacy() : MachineFunctionPass(ID) {
+ initializeMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry());
}
-void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
+void MachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
@@ -289,23 +339,24 @@ void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-char PostMachineScheduler::ID = 0;
+char PostMachineSchedulerLegacy::ID = 0;
-char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
+char &llvm::PostMachineSchedulerID = PostMachineSchedulerLegacy::ID;
-INITIALIZE_PASS_BEGIN(PostMachineScheduler, "postmisched",
+INITIALIZE_PASS_BEGIN(PostMachineSchedulerLegacy, "postmisched",
"PostRA Machine Instruction Scheduler", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
-INITIALIZE_PASS_END(PostMachineScheduler, "postmisched",
+INITIALIZE_PASS_END(PostMachineSchedulerLegacy, "postmisched",
"PostRA Machine Instruction Scheduler", false, false)
-PostMachineScheduler::PostMachineScheduler() : MachineSchedulerBase(ID) {
- initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
+PostMachineSchedulerLegacy::PostMachineSchedulerLegacy()
+ : MachineFunctionPass(ID) {
+ initializePostMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry());
}
-void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
+void PostMachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
@@ -385,17 +436,14 @@ nextIfDebug(MachineBasicBlock::iterator I,
}
/// Instantiate a ScheduleDAGInstrs that will be owned by the caller.
-ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
+ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() {
// Select the scheduler, or set the default.
MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
if (Ctor != useDefaultMachineSched)
return Ctor(this);
- const TargetMachine &TM =
- getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
-
// Get the default scheduler set by the target for this function.
- ScheduleDAGInstrs *Scheduler = TM.createMachineScheduler(this);
+ ScheduleDAGInstrs *Scheduler = TM->createMachineScheduler(this);
if (Scheduler)
return Scheduler;
@@ -403,14 +451,47 @@ ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
return createGenericSchedLive(this);
}
+bool MachineSchedulerImpl::run(MachineFunction &Func, const TargetMachine &TM,
+ const RequiredAnalyses &Analyses) {
+ MF = &Func;
+ MLI = &Analyses.MLI;
+ MDT = &Analyses.MDT;
+ this->TM = &TM;
+ AA = &Analyses.AA;
+ LIS = &Analyses.LIS;
+
+ if (VerifyScheduling) {
+ LLVM_DEBUG(LIS->dump());
+ const char *MSchedBanner = "Before machine scheduling.";
+ if (P)
+ MF->verify(P, MSchedBanner, &errs());
+ else
+ MF->verify(*MFAM, MSchedBanner, &errs());
+ }
+ RegClassInfo->runOnMachineFunction(*MF);
+
+ // Instantiate the selected scheduler for this target, function, and
+ // optimization level.
+ std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
+ scheduleRegions(*Scheduler, false);
+
+ LLVM_DEBUG(LIS->dump());
+ if (VerifyScheduling) {
+ const char *MSchedBanner = "After machine scheduling.";
+ if (P)
+ MF->verify(P, MSchedBanner, &errs());
+ else
+ MF->verify(*MFAM, MSchedBanner, &errs());
+ }
+ return true;
+}
+
/// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
/// the caller. We don't have a command line option to override the postRA
/// scheduler. The Target must configure it.
-ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
- const TargetMachine &TM =
- getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+ScheduleDAGInstrs *PostMachineSchedulerImpl::createPostMachineScheduler() {
// Get the postRA scheduler set by the target for this function.
- ScheduleDAGInstrs *Scheduler = TM.createPostMachineScheduler(this);
+ ScheduleDAGInstrs *Scheduler = TM->createPostMachineScheduler(this);
if (Scheduler)
return Scheduler;
@@ -418,6 +499,37 @@ ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
return createGenericSchedPostRA(this);
}
+bool PostMachineSchedulerImpl::run(MachineFunction &Func,
+ const TargetMachine &TM,
+ const RequiredAnalyses &Analyses) {
+ MF = &Func;
+ MLI = &Analyses.MLI;
+ this->TM = &TM;
+ AA = &Analyses.AA;
+
+ if (VerifyScheduling) {
+ const char *PostMSchedBanner = "Before post machine scheduling.";
+ if (P)
+ MF->verify(P, PostMSchedBanner, &errs());
+ else
+ MF->verify(*MFAM, PostMSchedBanner, &errs());
+ }
+
+ // Instantiate the selected scheduler for this target, function, and
+ // optimization level.
+ std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
+ scheduleRegions(*Scheduler, true);
+
+ if (VerifyScheduling) {
+ const char *PostMSchedBanner = "After post machine scheduling.";
+ if (P)
+ MF->verify(P, PostMSchedBanner, &errs());
+ else
+ MF->verify(*MFAM, PostMSchedBanner, &errs());
+ }
+ return true;
+}
+
/// Top-level MachineScheduler pass driver.
///
/// Visit blocks in function order. Divide each block into scheduling regions
@@ -434,72 +546,112 @@ ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
/// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
/// design would be to split blocks at scheduling boundaries, but LLVM has a
/// general bias against block splitting purely for implementation simplicity.
-bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
- if (skipFunction(mf.getFunction()))
+bool MachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
return false;
if (EnableMachineSched.getNumOccurrences()) {
if (!EnableMachineSched)
return false;
- } else if (!mf.getSubtarget().enableMachineScheduler())
+ } else if (!MF.getSubtarget().enableMachineScheduler()) {
return false;
-
- LLVM_DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs()));
-
- // Initialize the context of the pass.
- MF = &mf;
- MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
-
- LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
-
- if (VerifyScheduling) {
- LLVM_DEBUG(LIS->dump());
- MF->verify(this, "Before machine scheduling.", &errs());
}
- RegClassInfo->runOnMachineFunction(*MF);
- // Instantiate the selected scheduler for this target, function, and
- // optimization level.
- std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
- scheduleRegions(*Scheduler, false);
+ LLVM_DEBUG(dbgs() << "Before MISched:\n"; MF.print(dbgs()));
- LLVM_DEBUG(LIS->dump());
- if (VerifyScheduling)
- MF->verify(this, "After machine scheduling.", &errs());
-...
[truncated]
|
|
@llvm/pr-subscribers-backend-arm Author: Akshat Oke (optimisan) Changes
Now the Impl class is a member of the legacy and new passes so that it is not reconstructed on every pass run. Patch is 65.59 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/126684.diff 56 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index 4762494e6ccb77d..42912cc9cb539aa 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -98,6 +98,10 @@
#include <vector>
namespace llvm {
+namespace impl_detail {
+class MachineSchedulerImpl;
+class PostMachineSchedulerImpl;
+} // namespace impl_detail
namespace MISched {
enum Direction {
@@ -1385,6 +1389,30 @@ std::unique_ptr<ScheduleDAGMutation>
createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI);
+class MachineSchedulerPass : public PassInfoMixin<MachineSchedulerPass> {
+ std::unique_ptr<impl_detail::MachineSchedulerImpl> Impl;
+ const TargetMachine *TM;
+
+public:
+ MachineSchedulerPass(const TargetMachine *TM);
+ MachineSchedulerPass(MachineSchedulerPass &&Other);
+ ~MachineSchedulerPass();
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
+class PostMachineSchedulerPass
+ : public PassInfoMixin<PostMachineSchedulerPass> {
+ std::unique_ptr<impl_detail::PostMachineSchedulerImpl> Impl;
+ const TargetMachine *TM;
+
+public:
+ PostMachineSchedulerPass(const TargetMachine *TM);
+ PostMachineSchedulerPass(PostMachineSchedulerPass &&Other);
+ ~PostMachineSchedulerPass();
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
} // end namespace llvm
#endif // LLVM_CODEGEN_MACHINESCHEDULER_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 6d74d7f24bf9a82..b8df4d1ecab1d0f 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -209,7 +209,7 @@ void initializeMachinePipelinerPass(PassRegistry &);
void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializeMachineRegionInfoPassPass(PassRegistry &);
void initializeMachineSanitizerBinaryMetadataPass(PassRegistry &);
-void initializeMachineSchedulerPass(PassRegistry &);
+void initializeMachineSchedulerLegacyPass(PassRegistry &);
void initializeMachineSinkingPass(PassRegistry &);
void initializeMachineTraceMetricsWrapperPassPass(PassRegistry &);
void initializeMachineUniformityInfoPrinterPassPass(PassRegistry &);
@@ -238,7 +238,7 @@ void initializePostDomPrinterWrapperPassPass(PassRegistry &);
void initializePostDomViewerWrapperPassPass(PassRegistry &);
void initializePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializePostInlineEntryExitInstrumenterPass(PassRegistry &);
-void initializePostMachineSchedulerPass(PassRegistry &);
+void initializePostMachineSchedulerLegacyPass(PassRegistry &);
void initializePostRAHazardRecognizerPass(PassRegistry &);
void initializePostRAMachineSinkingPass(PassRegistry &);
void initializePostRASchedulerLegacyPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 7f91dd7ebf49de9..1458318ff021a98 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -50,6 +50,7 @@
#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MachineVerifier.h"
#include "llvm/CodeGen/OptimizePHIs.h"
#include "llvm/CodeGen/PHIElimination.h"
@@ -960,7 +961,7 @@ Error CodeGenPassBuilder<Derived, TargetMachineT>::addMachinePasses(
if (getOptLevel() != CodeGenOptLevel::None &&
!TM.targetSchedulesPostRAScheduling()) {
if (Opt.MISchedPostRA)
- addPass(PostMachineSchedulerPass());
+ addPass(PostMachineSchedulerPass(&TM));
else
addPass(PostRASchedulerPass(&TM));
}
@@ -1144,7 +1145,7 @@ void CodeGenPassBuilder<Derived, TargetMachineT>::addOptimizedRegAlloc(
addPass(RenameIndependentSubregsPass());
// PreRA instruction scheduling.
- addPass(MachineSchedulerPass());
+ addPass(MachineSchedulerPass(&TM));
if (derived().addRegAssignmentOptimized(addPass)) {
// Allow targets to expand pseudo instructions depending on the choice of
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 9f9922dfa5673c7..075ebcb82955329 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -142,12 +142,14 @@ MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass())
MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass())
MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass())
MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass())
+MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass(TM))
MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass())
MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass())
MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass())
MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass())
MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass())
MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass(TM))
+MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass(TM))
MACHINE_FUNCTION_PASS("print", PrintMIRPass())
MACHINE_FUNCTION_PASS("print<livedebugvars>", LiveDebugVariablesPrinterPass(errs()))
MACHINE_FUNCTION_PASS("print<live-intervals>", LiveIntervalsPrinterPass(errs()))
@@ -243,13 +245,11 @@ DUMMY_MACHINE_FUNCTION_PASS("static-data-splitter", StaticDataSplitter)
DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata)
-DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass)
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass)
-DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass)
DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles", MachineCycleInfoPrinterPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index d69a24f00871eac..35df2a479a545e7 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -94,7 +94,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeModuloScheduleTestPass(Registry);
initializeMachinePostDominatorTreeWrapperPassPass(Registry);
initializeMachineRegionInfoPassPass(Registry);
- initializeMachineSchedulerPass(Registry);
+ initializeMachineSchedulerLegacyPass(Registry);
initializeMachineSinkingPass(Registry);
initializeMachineUniformityAnalysisPassPass(Registry);
initializeMachineUniformityInfoPrinterPassPass(Registry);
@@ -105,7 +105,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePHIEliminationPass(Registry);
initializePatchableFunctionPass(Registry);
initializePeepholeOptimizerLegacyPass(Registry);
- initializePostMachineSchedulerPass(Registry);
+ initializePostMachineSchedulerLegacyPass(Registry);
initializePostRAHazardRecognizerPass(Registry);
initializePostRAMachineSinkingPass(Registry);
initializePostRASchedulerLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 3f72e8486c06ef8..1be7a33720dbfd5 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -214,69 +214,119 @@ MachineSchedContext::~MachineSchedContext() {
delete RegClassInfo;
}
-namespace {
-
-/// Base class for a machine scheduler class that can run at any point.
-class MachineSchedulerBase : public MachineSchedContext,
- public MachineFunctionPass {
-public:
- MachineSchedulerBase(char &ID) : MachineFunctionPass(ID) {}
+namespace llvm {
+namespace impl_detail {
+/// Base class for the machine scheduler classes.
+class MachineSchedulerBase : public MachineSchedContext {
protected:
void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags);
};
-/// MachineScheduler runs after coalescing and before register allocation.
-class MachineScheduler : public MachineSchedulerBase {
-public:
- MachineScheduler();
+/// Impl class for MachineScheduler.
+class MachineSchedulerImpl : public MachineSchedulerBase {
+ // These are only for using MF.verify()
+ // remove when verify supports passing in all analyses
+ MachineFunctionPass *P = nullptr;
+ MachineFunctionAnalysisManager *MFAM = nullptr;
- void getAnalysisUsage(AnalysisUsage &AU) const override;
+public:
+ struct RequiredAnalyses {
+ MachineLoopInfo &MLI;
+ MachineDominatorTree &MDT;
+ AAResults &AA;
+ LiveIntervals &LIS;
+ };
- bool runOnMachineFunction(MachineFunction&) override;
+ MachineSchedulerImpl() {}
+ // Migration only
+ void setLegacyPass(MachineFunctionPass *P) { this->P = P; }
+ void setMFAM(MachineFunctionAnalysisManager *MFAM) { this->MFAM = MFAM; }
- static char ID; // Class identification, replacement for typeinfo
+ bool run(MachineFunction &MF, const TargetMachine &TM,
+ const RequiredAnalyses &Analyses);
protected:
ScheduleDAGInstrs *createMachineScheduler();
};
-/// PostMachineScheduler runs after shortly before code emission.
-class PostMachineScheduler : public MachineSchedulerBase {
+/// Impl class for PostMachineScheduler.
+class PostMachineSchedulerImpl : public MachineSchedulerBase {
+ // These are only for using MF.verify()
+ // remove when verify supports passing in all analyses
+ MachineFunctionPass *P = nullptr;
+ MachineFunctionAnalysisManager *MFAM = nullptr;
+
public:
- PostMachineScheduler();
+ struct RequiredAnalyses {
+ MachineLoopInfo &MLI;
+ AAResults &AA;
+ };
+ PostMachineSchedulerImpl() {}
+ // Migration only
+ void setLegacyPass(MachineFunctionPass *P) { this->P = P; }
+ void setMFAM(MachineFunctionAnalysisManager *MFAM) { this->MFAM = MFAM; }
- void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool run(MachineFunction &Func, const TargetMachine &TM,
+ const RequiredAnalyses &Analyses);
+
+protected:
+ ScheduleDAGInstrs *createPostMachineScheduler();
+};
+} // namespace impl_detail
+} // namespace llvm
+
+using impl_detail::MachineSchedulerBase;
+using impl_detail::MachineSchedulerImpl;
+using impl_detail::PostMachineSchedulerImpl;
+
+namespace {
+/// MachineScheduler runs after coalescing and before register allocation.
+class MachineSchedulerLegacy : public MachineFunctionPass {
+ MachineSchedulerImpl Impl;
+
+public:
+ MachineSchedulerLegacy();
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
bool runOnMachineFunction(MachineFunction&) override;
static char ID; // Class identification, replacement for typeinfo
+};
-protected:
- ScheduleDAGInstrs *createPostMachineScheduler();
+/// PostMachineScheduler runs after shortly before code emission.
+class PostMachineSchedulerLegacy : public MachineFunctionPass {
+ PostMachineSchedulerImpl Impl;
+
+public:
+ PostMachineSchedulerLegacy();
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool runOnMachineFunction(MachineFunction &) override;
+
+ static char ID; // Class identification, replacement for typeinfo
};
} // end anonymous namespace
-char MachineScheduler::ID = 0;
+char MachineSchedulerLegacy::ID = 0;
-char &llvm::MachineSchedulerID = MachineScheduler::ID;
+char &llvm::MachineSchedulerID = MachineSchedulerLegacy::ID;
-INITIALIZE_PASS_BEGIN(MachineScheduler, DEBUG_TYPE,
+INITIALIZE_PASS_BEGIN(MachineSchedulerLegacy, DEBUG_TYPE,
"Machine Instruction Scheduler", false, false)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
-INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE,
+INITIALIZE_PASS_END(MachineSchedulerLegacy, DEBUG_TYPE,
"Machine Instruction Scheduler", false, false)
-MachineScheduler::MachineScheduler() : MachineSchedulerBase(ID) {
- initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
+MachineSchedulerLegacy::MachineSchedulerLegacy() : MachineFunctionPass(ID) {
+ initializeMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry());
}
-void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
+void MachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
@@ -289,23 +339,24 @@ void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-char PostMachineScheduler::ID = 0;
+char PostMachineSchedulerLegacy::ID = 0;
-char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
+char &llvm::PostMachineSchedulerID = PostMachineSchedulerLegacy::ID;
-INITIALIZE_PASS_BEGIN(PostMachineScheduler, "postmisched",
+INITIALIZE_PASS_BEGIN(PostMachineSchedulerLegacy, "postmisched",
"PostRA Machine Instruction Scheduler", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
-INITIALIZE_PASS_END(PostMachineScheduler, "postmisched",
+INITIALIZE_PASS_END(PostMachineSchedulerLegacy, "postmisched",
"PostRA Machine Instruction Scheduler", false, false)
-PostMachineScheduler::PostMachineScheduler() : MachineSchedulerBase(ID) {
- initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
+PostMachineSchedulerLegacy::PostMachineSchedulerLegacy()
+ : MachineFunctionPass(ID) {
+ initializePostMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry());
}
-void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
+void PostMachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
@@ -385,17 +436,14 @@ nextIfDebug(MachineBasicBlock::iterator I,
}
/// Instantiate a ScheduleDAGInstrs that will be owned by the caller.
-ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
+ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() {
// Select the scheduler, or set the default.
MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
if (Ctor != useDefaultMachineSched)
return Ctor(this);
- const TargetMachine &TM =
- getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
-
// Get the default scheduler set by the target for this function.
- ScheduleDAGInstrs *Scheduler = TM.createMachineScheduler(this);
+ ScheduleDAGInstrs *Scheduler = TM->createMachineScheduler(this);
if (Scheduler)
return Scheduler;
@@ -403,14 +451,47 @@ ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
return createGenericSchedLive(this);
}
+bool MachineSchedulerImpl::run(MachineFunction &Func, const TargetMachine &TM,
+ const RequiredAnalyses &Analyses) {
+ MF = &Func;
+ MLI = &Analyses.MLI;
+ MDT = &Analyses.MDT;
+ this->TM = &TM;
+ AA = &Analyses.AA;
+ LIS = &Analyses.LIS;
+
+ if (VerifyScheduling) {
+ LLVM_DEBUG(LIS->dump());
+ const char *MSchedBanner = "Before machine scheduling.";
+ if (P)
+ MF->verify(P, MSchedBanner, &errs());
+ else
+ MF->verify(*MFAM, MSchedBanner, &errs());
+ }
+ RegClassInfo->runOnMachineFunction(*MF);
+
+ // Instantiate the selected scheduler for this target, function, and
+ // optimization level.
+ std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
+ scheduleRegions(*Scheduler, false);
+
+ LLVM_DEBUG(LIS->dump());
+ if (VerifyScheduling) {
+ const char *MSchedBanner = "After machine scheduling.";
+ if (P)
+ MF->verify(P, MSchedBanner, &errs());
+ else
+ MF->verify(*MFAM, MSchedBanner, &errs());
+ }
+ return true;
+}
+
/// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
/// the caller. We don't have a command line option to override the postRA
/// scheduler. The Target must configure it.
-ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
- const TargetMachine &TM =
- getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+ScheduleDAGInstrs *PostMachineSchedulerImpl::createPostMachineScheduler() {
// Get the postRA scheduler set by the target for this function.
- ScheduleDAGInstrs *Scheduler = TM.createPostMachineScheduler(this);
+ ScheduleDAGInstrs *Scheduler = TM->createPostMachineScheduler(this);
if (Scheduler)
return Scheduler;
@@ -418,6 +499,37 @@ ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
return createGenericSchedPostRA(this);
}
+bool PostMachineSchedulerImpl::run(MachineFunction &Func,
+ const TargetMachine &TM,
+ const RequiredAnalyses &Analyses) {
+ MF = &Func;
+ MLI = &Analyses.MLI;
+ this->TM = &TM;
+ AA = &Analyses.AA;
+
+ if (VerifyScheduling) {
+ const char *PostMSchedBanner = "Before post machine scheduling.";
+ if (P)
+ MF->verify(P, PostMSchedBanner, &errs());
+ else
+ MF->verify(*MFAM, PostMSchedBanner, &errs());
+ }
+
+ // Instantiate the selected scheduler for this target, function, and
+ // optimization level.
+ std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
+ scheduleRegions(*Scheduler, true);
+
+ if (VerifyScheduling) {
+ const char *PostMSchedBanner = "After post machine scheduling.";
+ if (P)
+ MF->verify(P, PostMSchedBanner, &errs());
+ else
+ MF->verify(*MFAM, PostMSchedBanner, &errs());
+ }
+ return true;
+}
+
/// Top-level MachineScheduler pass driver.
///
/// Visit blocks in function order. Divide each block into scheduling regions
@@ -434,72 +546,112 @@ ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
/// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
/// design would be to split blocks at scheduling boundaries, but LLVM has a
/// general bias against block splitting purely for implementation simplicity.
-bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
- if (skipFunction(mf.getFunction()))
+bool MachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
return false;
if (EnableMachineSched.getNumOccurrences()) {
if (!EnableMachineSched)
return false;
- } else if (!mf.getSubtarget().enableMachineScheduler())
+ } else if (!MF.getSubtarget().enableMachineScheduler()) {
return false;
-
- LLVM_DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs()));
-
- // Initialize the context of the pass.
- MF = &mf;
- MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
-
- LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
-
- if (VerifyScheduling) {
- LLVM_DEBUG(LIS->dump());
- MF->verify(this, "Before machine scheduling.", &errs());
}
- RegClassInfo->runOnMachineFunction(*MF);
- // Instantiate the selected scheduler for this target, function, and
- // optimization level.
- std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
- scheduleRegions(*Scheduler, false);
+ LLVM_DEBUG(dbgs() << "Before MISched:\n"; MF.print(dbgs()));
- LLVM_DEBUG(LIS->dump());
- if (VerifyScheduling)
- MF->verify(this, "After machine scheduling.", &errs());
-...
[truncated]
|
| else | ||
| MF->verify(*MFAM, MSchedBanner, &errs()); | ||
| } | ||
| RegClassInfo->runOnMachineFunction(*MF); |
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Could we add something like RegisterClassAnalysis?
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There is a patch to convert it into an analysis: #120690
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Do you mean something else?
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Never mind. We can keep the workaround currenty and migrate to analysis result once pr 120690 is merged.
|
|
||
| Impl->setMFAM(&MFAM); | ||
| bool Changed = Impl->run(MF, *TM, {MLI, AA}); | ||
| if (!Changed) |
| Impl->setMFAM(&MFAM); | ||
| bool Changed = Impl->run(MF, *TM, {MLI, MDT, AA, LIS}); | ||
| if (!Changed) | ||
| return PreservedAnalyses::all(); |
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Dead code? Impl->run always returns true.
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Probably should do this anyway, the scheduler could / should try harder to report no-op runs
arsenm
reviewed
Feb 11, 2025
Comment on lines
101
to
104
| namespace impl_detail { | ||
| class MachineSchedulerImpl; | ||
| class PostMachineSchedulerImpl; | ||
| } // namespace impl_detail |
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I don't think these should need to be exposed in the header
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I want these Impl classes to be members in the new pass in this header. (workaround for RegisterClassInfo not being an analysis yet)
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So we can drop this after the analysis change is made?
arsenm
reviewed
Feb 12, 2025
arsenm
approved these changes
Feb 12, 2025
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RegisterClassInfowas supposed to be kept alive between pass runs, which wasn't being done leading to recomputations increasing the compile time.Now the Impl class is a member of the legacy and new passes so that it is not reconstructed on every pass run.