Skip to content

[X86] Truncate i64 add/sub/mul arithmetic to i32 with known zeros in upper 32 bits #143313

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Draft
wants to merge 1 commit into
base: main
Choose a base branch
from
+51 −0
Draft

[X86] Truncate i64 add/sub/mul arithmetic to i32 with known zeros in upper 32 bits #143313

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
20 changes: 20 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -58070,8 +58070,28 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
EVT VT = N->getValueType(0);
SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
unsigned int Opcode = N->getOpcode();
SDLoc DL(N);

// Use a 32-bit add+zext if upper 33 bits known zero.
if (VT == MVT::i64 && Subtarget.is64Bit()) {
APInt HiMask = APInt::getHighBitsSet(64, 33);
if (DAG.MaskedValueIsZero(Op0, HiMask) &&
DAG.MaskedValueIsZero(Op1, HiMask)) {
SDValue LHS = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op0);
SDValue RHS = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
bool NSW = Op0->getFlags().hasNoSignedWrap();
bool NUW = Op0->getFlags().hasNoUnsignedWrap();
NSW = NSW & DAG.willNotOverflowAdd(true, LHS, RHS);
NUW = NUW & DAG.willNotOverflowAdd(false, LHS, RHS);
SDNodeFlags Flags;
Flags.setNoUnsignedWrap(NUW);
Flags.setNoSignedWrap(NSW);
SDValue Sum = DAG.getNode(Opcode, DL, MVT::i32, LHS, RHS, Flags);
return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Sum);
}
}

if (SDValue Select = pushAddIntoCmovOfConsts(N, DL, DAG, Subtarget))
return Select;

Expand Down
31 changes: 31 additions & 0 deletions llvm/test/CodeGen/X86/reduce-i64-add.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,31 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-linux -verify-machineinstrs | FileCheck %s --check-prefix=X64-LINUX
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s --check-prefix=X64-WIN32

define i64 @test1(i16 %x) nounwind {
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Isn't it already generated the same code? https://godbolt.org/z/9Tqxco1ve

; X86-LABEL: test1:
; X86: # %bb.0: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: addl $42, %eax
; X86-NEXT: movzwl %ax, %eax
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: retl
;
; X64-LINUX-LABEL: test1:
; X64-LINUX: # %bb.0: # %entry
; X64-LINUX-NEXT: addl $42, %edi
; X64-LINUX-NEXT: movzwl %di, %eax
; X64-LINUX-NEXT: retq
;
; X64-WIN32-LABEL: test1:
; X64-WIN32: # %bb.0: # %entry
; X64-WIN32-NEXT: # kill: def $cx killed $cx def $ecx
; X64-WIN32-NEXT: addl $42, %ecx
; X64-WIN32-NEXT: movzwl %cx, %eax
; X64-WIN32-NEXT: retq
entry:
%add = add nuw nsw i16 %x, 42
%conv = zext i16 %add to i64
ret i64 %conv
}