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[AMDGPU] Allow dpp in v_pk_fmac_f16 for GFX9 and GFX10 #144782

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Merged
merged 7 commits into from
Jun 24, 2025
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[AMDGPU] Allow dpp in v_pk_fmac_f16 for GFX9 and GFX10 #144782

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c51f487
[AMDGPU] Allow dpp in v_pk_fmac_f16 for GFX9 and GFX10
jwanggit86 Jun 18, 2025
76a36b2
for gfx9, use existing VOP2_Real_e32e64_gfx9
jwanggit86 Jun 19, 2025
e16fa23
for gfx10, use existing VOP2_Real_gfx10
jwanggit86 Jun 19, 2025
bccf7eb
Revert "for gfx10, use existing VOP2_Real_gfx10"
jwanggit86 Jun 23, 2025
e9acb6c
GFX9 has SDWA instruction while GFX10 does not. Add tests to
jwanggit86 Jun 23, 2025
ff2c368
(1) A new multiclass for gfx10 (2) tests for disassembler
jwanggit86 Jun 23, 2025
39fcf97
Combine two defs into one
jwanggit86 Jun 24, 2025
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14 changes: 10 additions & 4 deletions llvm/lib/Target/AMDGPU/VOP2Instructions.td
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Expand Up @@ -1945,6 +1945,14 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then
def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")>;
}
multiclass VOP2Only_Real_e32_gfx10<bits<6> op> {
let IsSingle = 1 in
defm NAME: VOP2_Real_e32_gfx10<op>;
}
multiclass VOP2_Real_e32_dpp_dpp8_gfx10<bits<6> op> :
VOP2Only_Real_e32_gfx10<op>,
VOP2_Real_dpp_gfx10<op>,
VOP2_Real_dpp8_gfx10<op>;

//===------------------------- VOP2 (with name) -------------------------===//
multiclass VOP2_Real_e32_gfx10_with_name<bits<6> op, string opName,
Expand Down Expand Up @@ -2168,10 +2176,7 @@ defm V_FMAAK_F16 : VOP2Only_Real_MADK_gfx10<0x038>;
defm V_MAX_F16 : VOP2_Real_gfx10<0x039>;
defm V_MIN_F16 : VOP2_Real_gfx10<0x03a>;
defm V_LDEXP_F16 : VOP2_Real_gfx10<0x03b>;

let IsSingle = 1 in {
defm V_PK_FMAC_F16 : VOP2_Real_e32_gfx10<0x03c>;
}
defm V_PK_FMAC_F16 : VOP2_Real_e32_dpp_dpp8_gfx10<0x03c>;

// VOP2 no carry-in, carry-out.
defm V_ADD_NC_U32 :
Expand Down Expand Up @@ -2560,6 +2565,7 @@ defm V_SUBBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_s
defm V_ADD_U32 : VOP2_Real_e32e64_gfx9 <0x34>;
defm V_SUB_U32 : VOP2_Real_e32e64_gfx9 <0x35>;
defm V_SUBREV_U32 : VOP2_Real_e32e64_gfx9 <0x36>;
defm V_PK_FMAC_F16 : VOP2_Real_e32e64_gfx9<0x03c>;
} // End AssemblerPredicate = isGFX9Only

defm V_BFM_B32 : VOP2_Real_e64only_vi <0x293>;
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
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Expand Up @@ -13185,3 +13185,15 @@ v_pk_fmac_f16 v5, -4.0, v2

v_pk_fmac_f16 v5, v1, v255
// GFX10: encoding: [0x01,0xff,0x0b,0x78]

v_pk_fmac_f16 v5, v1, v2
// GFX10: encoding: [0x01,0x05,0x0a,0x78]

v_pk_fmac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3]
// GFX10: encoding: [0xfa,0x04,0x0a,0x78,0x01,0xe4,0x00,0xff]

v_pk_fmac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
// GFX10: encoding: [0xfa,0x04,0x0a,0x78,0x01,0xe4,0x00,0x00]

v_pk_fmac_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX10: encoding: [0xe9,0x04,0x0a,0x78,0x01,0x77,0x39,0x05]
3 changes: 3 additions & 0 deletions llvm/test/MC/AMDGPU/gfx10_unsupported_sdwa.s
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Expand Up @@ -32,6 +32,9 @@ v_min_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD s
v_mul_lo_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported

v_pk_fmac_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported

v_sub_co_u32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported

Expand Down
91 changes: 91 additions & 0 deletions llvm/test/MC/AMDGPU/gfx9_asm_vop2_features.s
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@@ -0,0 +1,91 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck --check-prefix=CHECK-MI %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck --check-prefix=CHECK-MI %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx942 -show-encoding %s | FileCheck --check-prefix=CHECK-MI %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx950 -show-encoding %s | FileCheck --check-prefix=CHECK-MI %s

v_pk_fmac_f16 v5, v1, v2
// CHECK-MI: [0x01,0x05,0x0a,0x78]

v_pk_fmac_f16 v5, v1, v2 quad_perm:[0,1,2,3]
// CHECK-MI: [0xfa,0x04,0x0a,0x78,0x01,0xe4,0x00,0xff]

v_pk_fmac_f16 v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
// CHECK-MI: [0xfa,0x04,0x0a,0x78,0x01,0xe4,0x00,0x00]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x00,0x06,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x01,0x06,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x02,0x06,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x03,0x06,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x04,0x06,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x05,0x06,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x0e,0x06,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x16,0x06,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x16,0x06,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x00,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x01,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x02,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x03,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x04,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x05,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x06]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x00]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x01]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x02]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x03]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x04]

v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x05]

v_pk_fmac_f16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// CHECK-MI: [0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x16]
7 changes: 7 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp16.txt
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Expand Up @@ -2476,3 +2476,10 @@
# W32: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff]
# W64: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff]
0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff

# GFX10: v_pk_fmac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x78,0x01,0xe4,0x00,0xff]
0xfa,0x04,0x0a,0x78,0x01,0xe4,0x00,0xff

# GFX10: v_pk_fmac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x78,0x01,0xe4,0x00,0x00]
0xfa,0x04,0x0a,0x78,0x01,0xe4,0x00,0x00

3 changes: 3 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp8.txt
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Expand Up @@ -222,3 +222,6 @@
# W32: v_cndmask_b32_dpp v0, v1, v2, vcc_lo dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x04,0x00,0x02,0x01,0x88,0xc6,0xfa]
# W64: v_cndmask_b32_dpp v0, v1, v2, vcc dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x04,0x00,0x02,0x01,0x88,0xc6,0xfa]
0xea,0x04,0x00,0x02,0x01,0x88,0xc6,0xfa

# GFX10: v_pk_fmac_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x78,0x01,0x77,0x39,0x05]
0xe9,0x04,0x0a,0x78,0x01,0x77,0x39,0x05
92 changes: 92 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_features.txt
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@@ -0,0 +1,92 @@
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx908 -disassemble -show-encoding < %s | FileCheck -check-prefix=CHECK-MI %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -disassemble -show-encoding < %s | FileCheck -check-prefix=CHECK-MI %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx942 -disassemble -show-encoding < %s | FileCheck -check-prefix=CHECK-MI %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx950 -disassemble -show-encoding < %s | FileCheck -check-prefix=CHECK-MI %s

# CHECK-MI: v_pk_fmac_f16_e32 v5, v1, v2
0x01,0x05,0x0a,0x78

# CHECK-MI: v_pk_fmac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf
0xfa,0x04,0x0a,0x78,0x01,0xe4,0x00,0xff

# CHECK-MI: v_pk_fmac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
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sdwa disasm tests needed.

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Done.

0xfa,0x04,0x0a,0x78,0x01,0xe4,0x00,0x00

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x00,0x06,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x01,0x06,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x02,0x06,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x03,0x06,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x04,0x06,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x05,0x06,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x0e,0x06,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x16,0x06,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x16,0x06,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x06,0x00,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x06,0x01,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x06,0x02,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x06,0x03,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x06,0x04,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x06,0x05,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x06

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x00

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x01

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x02

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x03

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x04

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x05

# CHECK-MI: v_pk_fmac_f16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
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This is the test case that is causing me problems (see my other comment). I would expect to see only a neg modifier (or -v2) on this instruction. But the corresponding assembly test in llvm/test/MC/AMDGPU/gfx9_asm_vop2_features.s confirms that the instruction is printed by AMDGPUInstPrinter::printOperandAndIntInputMods instead of MDGPUInstPrinter::printOperandAndFPInputMods as I would expect.

0xf9,0x04,0x0a,0x78,0x01,0x06,0x06,0x16