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[CIR] Upstream support for builtin_vectorelements #144877

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Merged
AmrDeveloper merged 1 commit into from
Jun 25, 2025
Merged

[CIR] Upstream support for builtin_vectorelements #144877

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7 changes: 0 additions & 7 deletions clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1914,13 +1914,6 @@ mlir::Value ScalarExprEmitter::VisitUnaryExprOrTypeTraitExpr(
return builder.getConstant(
loc, builder.getAttr<cir::IntAttr>(
cgf.cgm.UInt64Ty, llvm::APSInt(llvm::APInt(64, 1), true)));
} else if (e->getKind() == UETT_VectorElements) {
cgf.getCIRGenModule().errorNYI(e->getSourceRange(),
"sizeof operator for VectorElements",
e->getStmtClassName());
return builder.getConstant(
loc, builder.getAttr<cir::IntAttr>(
cgf.cgm.UInt64Ty, llvm::APSInt(llvm::APInt(64, 1), true)));
}

return builder.getConstant(
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15 changes: 15 additions & 0 deletions clang/test/CIR/CodeGen/vector-ext.cpp
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Expand Up @@ -1161,3 +1161,18 @@ void foo20() {
// OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[VEC_A]], align 16
// OGCG: %[[TMP_B:.*]] = load <4 x i32>, ptr %[[VEC_B]], align 16
// OGCG: %[[SHUF:.*]] = shufflevector <4 x i32> %[[TMP_A]], <4 x i32> %[[TMP_B]], <4 x i32> <i32 poison, i32 1, i32 poison, i32 1>

void foo21() {
vi4 a;
unsigned long size = __builtin_vectorelements(a);
}

// CIR: %[[INIT:.*]] = cir.alloca !u64i, !cir.ptr<!u64i>, ["size", init]
// CIR: %[[SIZE:.*]] = cir.const #cir.int<4> : !u64i
// CIR: cir.store align(8) %[[SIZE]], %[[INIT]] : !u64i, !cir.ptr<!u64i>

// LLVM: %[[SIZE:.*]] = alloca i64, i64 1, align 8
// LLVM: store i64 4, ptr %[[SIZE]], align 8

// OGCG: %[[SIZE:.*]] = alloca i64, align 8
// OGCG: store i64 4, ptr %[[SIZE]], align 8
15 changes: 15 additions & 0 deletions clang/test/CIR/CodeGen/vector.cpp
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Expand Up @@ -1203,3 +1203,18 @@ void foo23() {
// OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[VEC_A]], align 16
// OGCG: %[[TMP_B:.*]] = load <4 x i32>, ptr %[[VEC_B]], align 16
// OGCG: %[[SHUF:.*]] = shufflevector <4 x i32> %[[TMP_A]], <4 x i32> %[[TMP_B]], <4 x i32> <i32 poison, i32 1, i32 poison, i32 1>

void foo24() {
vi4 a;
unsigned long size = __builtin_vectorelements(a);
}

// CIR: %[[INIT:.*]] = cir.alloca !u64i, !cir.ptr<!u64i>, ["size", init]
// CIR: %[[SIZE:.*]] = cir.const #cir.int<4> : !u64i
// CIR: cir.store align(8) %[[SIZE]], %[[INIT]] : !u64i, !cir.ptr<!u64i>

// LLVM: %[[SIZE:.*]] = alloca i64, i64 1, align 8
// LLVM: store i64 4, ptr %[[SIZE]], align 8

// OGCG: %[[SIZE:.*]] = alloca i64, align 8
// OGCG: store i64 4, ptr %[[SIZE]], align 8
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