Skip to content

[MLIR][AArch64] Simplify LowerContractionToSVEI8MMPattern.cpp:getExtOperand (NFC) #144909

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: main
Choose a base branch
from
Open

[MLIR][AArch64] Simplify LowerContractionToSVEI8MMPattern.cpp:getExtOperand (NFC) #144909

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
20 changes: 8 additions & 12 deletions mlir/lib/Dialect/ArmSVE/Transforms/LowerContractionToSVEI8MMPattern.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ namespace {
//
// Return success only for extensions from `i8` to `i32`.
template <typename Op>
std::optional<Value> getExtOperand(Value v, Type i8Ty, Type i32Ty) {
std::optional<Value> getExtOperand(Value v) {

static_assert(llvm::is_one_of<Op, arith::ExtSIOp, arith::ExtUIOp>::value,
"Must be instantiated with either sign- or zero- extension op");
Expand All @@ -50,7 +50,7 @@ std::optional<Value> getExtOperand(Value v, Type i8Ty, Type i32Ty) {
if (!extOp) {
if constexpr (std::is_same<Op, arith::ExtSIOp>::value) {
auto vTy = cast<VectorType>(v.getType());
if (vTy.getElementType() != i8Ty)
if (!vTy.getElementType().isSignlessInteger(8))
return {};
return v;
}
Expand All @@ -61,11 +61,11 @@ std::optional<Value> getExtOperand(Value v, Type i8Ty, Type i32Ty) {
// operation type, check it's extended from `i8` to `i32`.
auto inOp = extOp.getIn();
auto inTy = dyn_cast<VectorType>(inOp.getType());
if (!inTy || inTy.getElementType() != i8Ty)
if (!inTy || !inTy.getElementType().isSignlessInteger(8))
return {};

auto outTy = dyn_cast<VectorType>(extOp.getType());
if (!outTy || outTy.getElementType() != i32Ty)
if (!outTy || !outTy.getElementType().isSignlessInteger(32))
return {};

return inOp;
Expand Down Expand Up @@ -199,27 +199,23 @@ class LowerContractionToSVEI8MMPattern
// operands are supported, but they are lowered to different operations.
// Determine which is the appropriate operation to lower to.
MMLA mmlaOp = MMLA::Signed;
auto maybeLhs = getExtOperand<arith::ExtSIOp>(
op.getLhs(), rewriter.getI8Type(), rewriter.getI32Type());
auto maybeLhs = getExtOperand<arith::ExtSIOp>(op.getLhs());
if (!maybeLhs) {
mmlaOp = MMLA::Unsigned;
maybeLhs = getExtOperand<arith::ExtUIOp>(
op.getLhs(), rewriter.getI8Type(), rewriter.getI32Type());
maybeLhs = getExtOperand<arith::ExtUIOp>(op.getLhs());
}
if (!maybeLhs)
return rewriter.notifyMatchFailure(
op, "LHS is not a sign- or zero- extended i8");

auto maybeRhs = getExtOperand<arith::ExtSIOp>(
op.getRhs(), rewriter.getI8Type(), rewriter.getI32Type());
auto maybeRhs = getExtOperand<arith::ExtSIOp>(op.getRhs());
if (maybeRhs) {
if (mmlaOp == MMLA::Unsigned)
mmlaOp = MMLA::Mixed;
} else {
if (mmlaOp == MMLA::Signed)
mmlaOp = MMLA::MixedSwapped;
maybeRhs = getExtOperand<arith::ExtUIOp>(
op.getRhs(), rewriter.getI8Type(), rewriter.getI32Type());
maybeRhs = getExtOperand<arith::ExtUIOp>(op.getRhs());
}
if (!maybeRhs)
return rewriter.notifyMatchFailure(
Expand Down
Loading