[RISCV] Use Hints for Xqcisim/Xqcisync Aliases #151040
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My aim here is to make these a little easier to maintain by relying on aliases where these instructions overlap with the Hint instructions they are based on. The following instructions have not been converted to aliases as they have complex mappings from ther immediate encodings to the immediate encoding of the underlying instruction (setting high bits): - qc.pputci - qc.sync, qc.sync, qc.syncwf, qc.syncwl - qc.c.sync, qc.c.syncr, qc.c.syncwf, qc.syncwl Co-authored-by: Sudharsan Veeravalli <[email protected]>
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@llvm/pr-subscribers-backend-risc-v Author: Sam Elliott (lenary) ChangesMy aim here is to make these a little easier to maintain by relying on aliases where these instructions overlap with the Hint instructions they are based on. The following instructions have not been converted to aliases as they have complex mappings from ther immediate encodings to the immediate encoding of the underlying instruction (setting high bits):
Full diff: https://github.com/llvm/llvm-project/pull/151040.diff 3 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index f39130090defd..52656134b7774 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1120,27 +1120,11 @@ let Predicates = [HasVendorXqcisync, IsRV32] in {
def QC_C_SYNCWF : QCIRVInst16CBSYNC<0b100, "qc.c.syncwf">;
def QC_C_SYNCWL : QCIRVInst16CBSYNC<0b101, "qc.c.syncwl">;
- let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
- def QC_C_DELAY : RVInst16CI<0b000, 0b10, (outs),
- (ins uimm5nonzero:$imm),
- "qc.c.delay", "$imm"> {
- let Inst{12} = 0;
- let Inst{11-7} = 0;
- let Inst{6-2} = imm{4-0};
- }
+ // qc.c.delay implemented as an alias, below
} // Predicates = [HasVendorXqcisync, IsRV32]
let Predicates = [HasVendorXqcisim, IsRV32] in {
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
- def QC_PSYSCALLI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm10:$imm10),
- "qc.psyscalli", "$imm10"> {
- bits<10> imm10;
-
- let rs1 = 0;
- let rd = 0;
- let imm12 = {0b00, imm10};
- }
-
def QC_PPUTCI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm8:$imm8),
"qc.pputci", "$imm8"> {
bits<8> imm8;
@@ -1150,18 +1134,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
let imm12 = {0b0100, imm8};
}
- def QC_PCOREDUMP : QCISim_NONE<0b0110, "qc.pcoredump">;
- def QC_PPREGS : QCISim_NONE<0b0111, "qc.ppregs">;
- def QC_PPREG : QCISim_RS1<0b1000, "qc.ppreg">;
- def QC_PPUTC : QCISim_RS1<0b1001, "qc.pputc">;
- def QC_PPUTS : QCISim_RS1<0b1010, "qc.pputs">;
- def QC_PEXIT : QCISim_RS1<0b1011, "qc.pexit">;
- def QC_PSYSCALL : QCISim_RS1<0b1100, "qc.psyscall">;
-
- def QC_C_PTRACE : RVInst16CI<0b000, 0b10, (outs), (ins), "qc.c.ptrace", ""> {
- let rd = 0;
- let imm = 0;
- }
+ // The other instructions are all implemented as aliases, below
} // mayLoad = 0, mayStore = 0, hasSideEffects = 1
} // Predicates = [HasVendorXqcisim, IsRV32]
@@ -1218,6 +1191,27 @@ let EmitPriority = 0 in {
} // EmitPriority = 0
} // Predicates = [HasVendorXqcilo, IsRV32]
+let Predicates = [HasVendorXqcisim, IsRV32] in {
+let EmitPriority = 1 in {
+ def : InstAlias<"qc.c.ptrace", (C_SLLI X0, 0)>;
+
+ def : InstAlias<"qc.psyscalli $imm", (SLTI X0, X0, uimm10:$imm)>;
+ def : InstAlias<"qc.pcoredump", (SLTI X0, X0, 1536)>;
+ def : InstAlias<"qc.ppregs", (SLTI X0, X0, 1792)>;
+ def : InstAlias<"qc.ppreg $rs1", (SLTI X0, GPR:$rs1, -2048)>;
+ def : InstAlias<"qc.pputc $rs1", (SLTI X0, GPR:$rs1, -1792)>;
+ def : InstAlias<"qc.pputs $rs1", (SLTI X0, GPR:$rs1, -1536)>;
+ def : InstAlias<"qc.pexit $rs1", (SLTI X0, GPR:$rs1, -1280)>;
+ def : InstAlias<"qc.psyscall $rs1", (SLTI X0, GPR:$rs1, -1024)>;
+} // EmitPriority = 1
+} // Predicates = [HasVendorXqcisim, IsRV32]
+
+let Predicates = [HasVendorXqcisync, IsRV32] in {
+let EmitPriority = 1 in {
+ def : InstAlias<"qc.c.delay $imm", (C_SLLI X0, uimm5nonzero:$imm)>;
+}
+} // Predicates = [HasVendorXqcisync, IsRV32]
+
//===----------------------------------------------------------------------===//
// Pseudo-instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/RISCV/xqcisim-valid.s b/llvm/test/MC/RISCV/xqcisim-valid.s
index b5758f451ed6d..ed8e1df0807ca 100644
--- a/llvm/test/MC/RISCV/xqcisim-valid.s
+++ b/llvm/test/MC/RISCV/xqcisim-valid.s
@@ -3,15 +3,16 @@
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisim < %s \
# RUN: | llvm-objdump --mattr=+experimental-xqcisim -M no-aliases --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-NOALIAS %s
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisim -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisim < %s \
# RUN: | llvm-objdump --mattr=+experimental-xqcisim --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ALIAS %s
-# CHECK-INST: qc.psyscalli 1023
+# CHECK-ALIAS: qc.psyscalli 1023
+# CHECK-NOINST: slti zero, zero, 1023
# CHECK-ENC: encoding: [0x13,0x20,0xf0,0x3f]
qc.psyscalli 1023
@@ -19,34 +20,42 @@ qc.psyscalli 1023
# CHECK-ENC: encoding: [0x13,0x20,0xf0,0x4f]
qc.pputci 255
-# CHECK-INST: qc.c.ptrace
+# CHECK-ALIAS: qc.c.ptrace
+# CHECK-NOALIAS: c.slli zero, 0
# CHECK-ENC: encoding: [0x02,0x00]
qc.c.ptrace
-# CHECK-INST: qc.pcoredump
+# CHECK-ALIAS: qc.pcoredump
+# CHECK-NOALIAS: slti zero, zero, 1536
# CHECK-ENC: encoding: [0x13,0x20,0x00,0x60]
qc.pcoredump
-# CHECK-INST: qc.ppregs
+# CHECK-ALIAS: qc.ppregs
+# CHECK-NOALIAS: slti zero, zero, 1792
# CHECK-ENC: encoding: [0x13,0x20,0x00,0x70]
qc.ppregs
-# CHECK-INST: qc.ppreg a0
+# CHECK-ALIAS: qc.ppreg a0
+# CHECK-NOALIAS: slti zero, a0, -2048
# CHECK-ENC: encoding: [0x13,0x20,0x05,0x80]
qc.ppreg x10
-# CHECK-INST: qc.pputc t2
+# CHECK-ALIAS: qc.pputc t2
+# CHECK-NOALIAS: slti zero, t2, -1792
# CHECK-ENC: encoding: [0x13,0xa0,0x03,0x90]
qc.pputc x7
-# CHECK-INST: qc.pputs a5
+# CHECK-ALIAS: qc.pputs a5
+# CHECK-NOALIAS: slti zero, a5, -1536
# CHECK-ENC: encoding: [0x13,0xa0,0x07,0xa0]
qc.pputs x15
-# CHECK-INST: qc.pexit s10
+# CHECK-ALIAS: qc.pexit s10
+# CHECK-NOALIAS: slti zero, s10, -1280
# CHECK-ENC: encoding: [0x13,0x20,0x0d,0xb0]
qc.pexit x26
-# CHECK-INST: qc.psyscall a1
+# CHECK-ALIAS: qc.psyscall a1
+# CHECK-NOALIAS: slti zero, a1, -1024
# CHECK-ENC: encoding: [0x13,0xa0,0x05,0xc0]
qc.psyscall x11
diff --git a/llvm/test/MC/RISCV/xqcisync-valid.s b/llvm/test/MC/RISCV/xqcisync-valid.s
index 84ea74b74564f..5b4c5061527c2 100644
--- a/llvm/test/MC/RISCV/xqcisync-valid.s
+++ b/llvm/test/MC/RISCV/xqcisync-valid.s
@@ -3,14 +3,15 @@
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisync < %s \
# RUN: | llvm-objdump --mattr=+experimental-xqcisync -M no-aliases --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-NOALIAS %s
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisync -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisync < %s \
# RUN: | llvm-objdump --mattr=+experimental-xqcisync --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ALIAS %s
-# CHECK-INST: qc.c.delay 10
+# CHECK-NOALIAS: c.slli zero, 10
+# CHECK-ALIAS: qc.c.delay 10
# CHECK-ENC: encoding: [0x2a,0x00]
qc.c.delay 10
|
|
@llvm/pr-subscribers-mc Author: Sam Elliott (lenary) ChangesMy aim here is to make these a little easier to maintain by relying on aliases where these instructions overlap with the Hint instructions they are based on. The following instructions have not been converted to aliases as they have complex mappings from ther immediate encodings to the immediate encoding of the underlying instruction (setting high bits):
Full diff: https://github.com/llvm/llvm-project/pull/151040.diff 3 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index f39130090defd..52656134b7774 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1120,27 +1120,11 @@ let Predicates = [HasVendorXqcisync, IsRV32] in {
def QC_C_SYNCWF : QCIRVInst16CBSYNC<0b100, "qc.c.syncwf">;
def QC_C_SYNCWL : QCIRVInst16CBSYNC<0b101, "qc.c.syncwl">;
- let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
- def QC_C_DELAY : RVInst16CI<0b000, 0b10, (outs),
- (ins uimm5nonzero:$imm),
- "qc.c.delay", "$imm"> {
- let Inst{12} = 0;
- let Inst{11-7} = 0;
- let Inst{6-2} = imm{4-0};
- }
+ // qc.c.delay implemented as an alias, below
} // Predicates = [HasVendorXqcisync, IsRV32]
let Predicates = [HasVendorXqcisim, IsRV32] in {
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
- def QC_PSYSCALLI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm10:$imm10),
- "qc.psyscalli", "$imm10"> {
- bits<10> imm10;
-
- let rs1 = 0;
- let rd = 0;
- let imm12 = {0b00, imm10};
- }
-
def QC_PPUTCI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm8:$imm8),
"qc.pputci", "$imm8"> {
bits<8> imm8;
@@ -1150,18 +1134,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
let imm12 = {0b0100, imm8};
}
- def QC_PCOREDUMP : QCISim_NONE<0b0110, "qc.pcoredump">;
- def QC_PPREGS : QCISim_NONE<0b0111, "qc.ppregs">;
- def QC_PPREG : QCISim_RS1<0b1000, "qc.ppreg">;
- def QC_PPUTC : QCISim_RS1<0b1001, "qc.pputc">;
- def QC_PPUTS : QCISim_RS1<0b1010, "qc.pputs">;
- def QC_PEXIT : QCISim_RS1<0b1011, "qc.pexit">;
- def QC_PSYSCALL : QCISim_RS1<0b1100, "qc.psyscall">;
-
- def QC_C_PTRACE : RVInst16CI<0b000, 0b10, (outs), (ins), "qc.c.ptrace", ""> {
- let rd = 0;
- let imm = 0;
- }
+ // The other instructions are all implemented as aliases, below
} // mayLoad = 0, mayStore = 0, hasSideEffects = 1
} // Predicates = [HasVendorXqcisim, IsRV32]
@@ -1218,6 +1191,27 @@ let EmitPriority = 0 in {
} // EmitPriority = 0
} // Predicates = [HasVendorXqcilo, IsRV32]
+let Predicates = [HasVendorXqcisim, IsRV32] in {
+let EmitPriority = 1 in {
+ def : InstAlias<"qc.c.ptrace", (C_SLLI X0, 0)>;
+
+ def : InstAlias<"qc.psyscalli $imm", (SLTI X0, X0, uimm10:$imm)>;
+ def : InstAlias<"qc.pcoredump", (SLTI X0, X0, 1536)>;
+ def : InstAlias<"qc.ppregs", (SLTI X0, X0, 1792)>;
+ def : InstAlias<"qc.ppreg $rs1", (SLTI X0, GPR:$rs1, -2048)>;
+ def : InstAlias<"qc.pputc $rs1", (SLTI X0, GPR:$rs1, -1792)>;
+ def : InstAlias<"qc.pputs $rs1", (SLTI X0, GPR:$rs1, -1536)>;
+ def : InstAlias<"qc.pexit $rs1", (SLTI X0, GPR:$rs1, -1280)>;
+ def : InstAlias<"qc.psyscall $rs1", (SLTI X0, GPR:$rs1, -1024)>;
+} // EmitPriority = 1
+} // Predicates = [HasVendorXqcisim, IsRV32]
+
+let Predicates = [HasVendorXqcisync, IsRV32] in {
+let EmitPriority = 1 in {
+ def : InstAlias<"qc.c.delay $imm", (C_SLLI X0, uimm5nonzero:$imm)>;
+}
+} // Predicates = [HasVendorXqcisync, IsRV32]
+
//===----------------------------------------------------------------------===//
// Pseudo-instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/RISCV/xqcisim-valid.s b/llvm/test/MC/RISCV/xqcisim-valid.s
index b5758f451ed6d..ed8e1df0807ca 100644
--- a/llvm/test/MC/RISCV/xqcisim-valid.s
+++ b/llvm/test/MC/RISCV/xqcisim-valid.s
@@ -3,15 +3,16 @@
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisim < %s \
# RUN: | llvm-objdump --mattr=+experimental-xqcisim -M no-aliases --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-NOALIAS %s
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisim -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisim < %s \
# RUN: | llvm-objdump --mattr=+experimental-xqcisim --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ALIAS %s
-# CHECK-INST: qc.psyscalli 1023
+# CHECK-ALIAS: qc.psyscalli 1023
+# CHECK-NOINST: slti zero, zero, 1023
# CHECK-ENC: encoding: [0x13,0x20,0xf0,0x3f]
qc.psyscalli 1023
@@ -19,34 +20,42 @@ qc.psyscalli 1023
# CHECK-ENC: encoding: [0x13,0x20,0xf0,0x4f]
qc.pputci 255
-# CHECK-INST: qc.c.ptrace
+# CHECK-ALIAS: qc.c.ptrace
+# CHECK-NOALIAS: c.slli zero, 0
# CHECK-ENC: encoding: [0x02,0x00]
qc.c.ptrace
-# CHECK-INST: qc.pcoredump
+# CHECK-ALIAS: qc.pcoredump
+# CHECK-NOALIAS: slti zero, zero, 1536
# CHECK-ENC: encoding: [0x13,0x20,0x00,0x60]
qc.pcoredump
-# CHECK-INST: qc.ppregs
+# CHECK-ALIAS: qc.ppregs
+# CHECK-NOALIAS: slti zero, zero, 1792
# CHECK-ENC: encoding: [0x13,0x20,0x00,0x70]
qc.ppregs
-# CHECK-INST: qc.ppreg a0
+# CHECK-ALIAS: qc.ppreg a0
+# CHECK-NOALIAS: slti zero, a0, -2048
# CHECK-ENC: encoding: [0x13,0x20,0x05,0x80]
qc.ppreg x10
-# CHECK-INST: qc.pputc t2
+# CHECK-ALIAS: qc.pputc t2
+# CHECK-NOALIAS: slti zero, t2, -1792
# CHECK-ENC: encoding: [0x13,0xa0,0x03,0x90]
qc.pputc x7
-# CHECK-INST: qc.pputs a5
+# CHECK-ALIAS: qc.pputs a5
+# CHECK-NOALIAS: slti zero, a5, -1536
# CHECK-ENC: encoding: [0x13,0xa0,0x07,0xa0]
qc.pputs x15
-# CHECK-INST: qc.pexit s10
+# CHECK-ALIAS: qc.pexit s10
+# CHECK-NOALIAS: slti zero, s10, -1280
# CHECK-ENC: encoding: [0x13,0x20,0x0d,0xb0]
qc.pexit x26
-# CHECK-INST: qc.psyscall a1
+# CHECK-ALIAS: qc.psyscall a1
+# CHECK-NOALIAS: slti zero, a1, -1024
# CHECK-ENC: encoding: [0x13,0xa0,0x05,0xc0]
qc.psyscall x11
diff --git a/llvm/test/MC/RISCV/xqcisync-valid.s b/llvm/test/MC/RISCV/xqcisync-valid.s
index 84ea74b74564f..5b4c5061527c2 100644
--- a/llvm/test/MC/RISCV/xqcisync-valid.s
+++ b/llvm/test/MC/RISCV/xqcisync-valid.s
@@ -3,14 +3,15 @@
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisync < %s \
# RUN: | llvm-objdump --mattr=+experimental-xqcisync -M no-aliases --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-NOALIAS %s
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisync -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisync < %s \
# RUN: | llvm-objdump --mattr=+experimental-xqcisync --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ALIAS %s
-# CHECK-INST: qc.c.delay 10
+# CHECK-NOALIAS: c.slli zero, 10
+# CHECK-ALIAS: qc.c.delay 10
# CHECK-ENC: encoding: [0x2a,0x00]
qc.c.delay 10
|
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My aim here is to make these a little easier to maintain by relying on aliases where these instructions overlap with the Hint instructions they are based on.
The following instructions have not been converted to aliases as they have complex mappings from ther immediate encodings to the immediate encoding of the underlying instruction (setting high bits):