[ROCDL] Added rocdl.fmed3 -> Intrinsic::amdgcn_fmed3 #159332
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Signed-off-by: keshavvinayak01 <[email protected]>
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@llvm/pr-subscribers-mlir @llvm/pr-subscribers-mlir-llvm Author: Keshav Vinayak Jha (keshavvinayak01) ChangesDescriptionAdded support for AMDGPU signed (med3) intrinsics. Implemented Testing
Addresses #157052 Full diff: https://github.com/llvm/llvm-project/pull/159332.diff 2 Files Affected:
diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
index 9fa3ec1fc4b21..1d31ec069b5c0 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -1291,6 +1291,26 @@ def ROCDL_CvtScaleF32PkFp4F32Op :
}];
}
+//===----------------------------------------------------------------------===//
+// MED3 operations
+//===----------------------------------------------------------------------===//
+
+def ROCDL_Med3Op : ROCDL_ConcreteNonMemIntrOp<"med3", [Pure, AllTypesMatch<["res", "src0", "src1", "src2"]>], 1>,
+ Arguments<(ins LLVM_ScalarOrVectorOf<LLVM_AnyFloat>:$src0,
+ LLVM_ScalarOrVectorOf<LLVM_AnyFloat>:$src1,
+ LLVM_ScalarOrVectorOf<LLVM_AnyFloat>:$src2)> {
+ let results = (outs LLVM_ScalarOrVectorOf<LLVM_AnyFloat>:$res);
+ let summary = "Median of three float/half values";
+ let assemblyFormat = [{
+ $src0 `,` $src1 `,` $src2 attr-dict `:` `(` type($src0) `,` type($src1) `,` type($src2) `)` `->` type($res)
+ }];
+ string llvmBuilder = [{
+ $res = createIntrinsicCall(builder, llvm::Intrinsic::amdgcn_fmed3,
+ {$src0, $src1, $src2},
+ {moduleTranslation.convertType(op.getRes().getType())});
+ }];
+}
+
//===----------------------------------------------------------------------===//
// ROCDL target attribute.
//===----------------------------------------------------------------------===//
diff --git a/mlir/test/Target/LLVMIR/rocdl.mlir b/mlir/test/Target/LLVMIR/rocdl.mlir
index a464358250c38..579669f646ceb 100644
--- a/mlir/test/Target/LLVMIR/rocdl.mlir
+++ b/mlir/test/Target/LLVMIR/rocdl.mlir
@@ -1298,6 +1298,20 @@ llvm.func @rocdl_last_use(%ptr: !llvm.ptr<1>) -> i32 {
llvm.return %ret : i32
}
+llvm.func @test_med3_f16(%arg0: f16, %arg1: f16, %arg2: f16) -> f16 {
+ // CHECK-LABEL: define half @test_med3_f16(half %0, half %1, half %2)
+ %0 = rocdl.med3 %arg0, %arg1, %arg2 : (f16, f16, f16) -> f16
+ llvm.return %0 : f16
+ // CHECK: call half @llvm.amdgcn.fmed3.f16(half %0, half %1, half %2)
+}
+
+llvm.func @test_med3_f32(%arg0: f32, %arg1: f32, %arg2: f32) -> f32 {
+ // CHECK-LABEL: define float @test_med3_f32(float %0, float %1, float %2)
+ %0 = rocdl.med3 %arg0, %arg1, %arg2 : (f32, f32, f32) -> f32
+ llvm.return %0 : f32
+ // CHECK: call float @llvm.amdgcn.fmed3.f32(float %0, float %1, float %2)
+}
+
// CHECK-DAG: attributes #[[$KERNEL_ATTRS]] = { "amdgpu-flat-work-group-size"="1,256" "uniform-work-group-size"="true" }
// CHECK-DAG: attributes #[[$KERNEL_WORKGROUP_ATTRS]] = { "amdgpu-flat-work-group-size"="1,1024"
// CHECK-DAG: attributes #[[$KNOWN_BLOCK_SIZE_ATTRS]] = { "amdgpu-flat-work-group-size"="128,128"
|
| let results = (outs LLVM_ScalarOrVectorOf<LLVM_AnyFloat>:$res); | ||
| let summary = "Median of three float/half values"; | ||
| let assemblyFormat = [{ | ||
| $src0 `,` $src1 `,` $src2 attr-dict `:` `(` type($src0) `,` type($src1) `,` type($src2) `)` `->` type($res) |
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I'd just use type($res) here - it simplifies the assembly format
| $src0 `,` $src1 `,` $src2 attr-dict `:` `(` type($src0) `,` type($src1) `,` type($src2) `)` `->` type($res) | ||
| }]; | ||
| string llvmBuilder = [{ | ||
| $res = createIntrinsicCall(builder, llvm::Intrinsic::amdgcn_fmed3, |
| {$src0, $src1, $src2}, | ||
| {moduleTranslation.convertType(op.getRes().getType())}); | ||
| }]; | ||
| } |
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While this dialect isn't a shining example of good practice historically, could we get a summary and some usage examples for the documentation?
Description
Added ROCDL fmed3 op to support rewrite to
amdgcn_fmed3intrinsic.Testing
rocdl.med3ops in/test/Target/LLVMIR/rocdl.mlirAddresses #157052