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[RISCV] For (2^N +/- 2^M) muls, prefer ADD to SUB #166757

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[RISCV] For (2^N +/- 2^M) muls, prefer ADD to SUB #166757

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8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16477,12 +16477,12 @@ static SDValue expandMulToAddOrSubOfShl(SDNode *N, SelectionDAG &DAG,
uint64_t MulAmtLowBit = MulAmt & (-MulAmt);
ISD::NodeType Op;
uint64_t ShiftAmt1;
if (isPowerOf2_64(MulAmt + MulAmtLowBit)) {
Op = ISD::SUB;
ShiftAmt1 = MulAmt + MulAmtLowBit;
} else if (isPowerOf2_64(MulAmt - MulAmtLowBit)) {
if (isPowerOf2_64(MulAmt - MulAmtLowBit)) {
Op = ISD::ADD;
ShiftAmt1 = MulAmt - MulAmtLowBit;
} else if (isPowerOf2_64(MulAmt + MulAmtLowBit)) {
Op = ISD::SUB;
ShiftAmt1 = MulAmt + MulAmtLowBit;
} else {
return SDValue();
}
Expand Down
56 changes: 28 additions & 28 deletions llvm/test/CodeGen/RISCV/mul.ll
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Expand Up @@ -1185,29 +1185,29 @@ define i32 @muli32_p384(i32 %a) nounwind {
; RV32I-LABEL: muli32_p384:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 7
; RV32I-NEXT: slli a0, a0, 9
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: slli a0, a0, 8
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IM-LABEL: muli32_p384:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a0, 7
; RV32IM-NEXT: slli a0, a0, 9
; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: slli a0, a0, 8
; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muli32_p384:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 7
; RV64I-NEXT: slli a0, a0, 9
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: slli a0, a0, 8
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_p384:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 7
; RV64IM-NEXT: slli a0, a0, 9
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 8
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 384
ret i32 %1
Expand All @@ -1217,29 +1217,29 @@ define i32 @muli32_p12288(i32 %a) nounwind {
; RV32I-LABEL: muli32_p12288:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 12
; RV32I-NEXT: slli a0, a0, 14
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: slli a0, a0, 13
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IM-LABEL: muli32_p12288:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a0, 12
; RV32IM-NEXT: slli a0, a0, 14
; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: slli a0, a0, 13
; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muli32_p12288:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 12
; RV64I-NEXT: slli a0, a0, 14
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: slli a0, a0, 13
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_p12288:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 12
; RV64IM-NEXT: slli a0, a0, 14
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 13
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 12288
ret i32 %1
Expand Down Expand Up @@ -2117,14 +2117,14 @@ define i64 @muland_demand(i64 %x) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: andi a0, a0, -8
; RV32IM-NEXT: slli a2, a1, 2
; RV32IM-NEXT: slli a1, a1, 4
; RV32IM-NEXT: sub a1, a1, a2
; RV32IM-NEXT: slli a1, a1, 3
; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: li a2, 12
; RV32IM-NEXT: mulhu a2, a0, a2
; RV32IM-NEXT: add a1, a2, a1
; RV32IM-NEXT: slli a2, a0, 2
; RV32IM-NEXT: slli a0, a0, 4
; RV32IM-NEXT: sub a0, a0, a2
; RV32IM-NEXT: slli a0, a0, 3
; RV32IM-NEXT: add a0, a0, a2
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muland_demand:
Expand All @@ -2133,16 +2133,16 @@ define i64 @muland_demand(i64 %x) nounwind {
; RV64I-NEXT: srli a1, a1, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a1, a0, 2
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: slli a0, a0, 3
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muland_demand:
; RV64IM: # %bb.0:
; RV64IM-NEXT: andi a0, a0, -8
; RV64IM-NEXT: slli a1, a0, 2
; RV64IM-NEXT: slli a0, a0, 4
; RV64IM-NEXT: sub a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 3
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
%and = and i64 %x, 4611686018427387896
%mul = mul i64 %and, 12
Expand Down Expand Up @@ -2171,15 +2171,15 @@ define i64 @mulzext_demand(i32 signext %x) nounwind {
; RV64I-LABEL: mulzext_demand:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 32
; RV64I-NEXT: slli a0, a0, 34
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: slli a0, a0, 33
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: mulzext_demand:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 32
; RV64IM-NEXT: slli a0, a0, 34
; RV64IM-NEXT: sub a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 33
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
%ext = zext i32 %x to i64
%mul = mul i64 %ext, 12884901888
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/pr145360.ll
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Expand Up @@ -27,11 +27,11 @@ define i32 @unsigned(i32 %0, ptr %1) {
; CHECK-NEXT: slli a4, a3, 32
; CHECK-NEXT: mulhu a2, a2, a4
; CHECK-NEXT: srli a2, a2, 36
; CHECK-NEXT: slli a4, a2, 5
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub a2, a2, a4
; CHECK-NEXT: slli a4, a2, 3
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: srliw a4, a0, 3
; CHECK-NEXT: add a2, a0, a2
; CHECK-NEXT: sub a2, a0, a2
; CHECK-NEXT: mulw a0, a4, a3
; CHECK-NEXT: sw a2, 0(a1)
; CHECK-NEXT: ret
Expand Down Expand Up @@ -68,10 +68,10 @@ define i32 @unsigned_div_first(i32 %0, ptr %1) {
; CHECK-NEXT: slli a3, a3, 32
; CHECK-NEXT: mulhu a2, a2, a3
; CHECK-NEXT: srli a2, a2, 36
; CHECK-NEXT: slli a3, a2, 5
; CHECK-NEXT: slli a4, a2, 3
; CHECK-NEXT: sub a4, a4, a3
; CHECK-NEXT: add a0, a0, a4
; CHECK-NEXT: slli a3, a2, 3
; CHECK-NEXT: slli a4, a2, 4
; CHECK-NEXT: add a3, a4, a3
; CHECK-NEXT: sub a0, a0, a3
; CHECK-NEXT: sw a0, 0(a1)
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: ret
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/rv32xtheadba.ll
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Expand Up @@ -98,8 +98,8 @@ define i32 @addmul6(i32 %a, i32 %b) {
; RV32I-LABEL: addmul6:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 1
; RV32I-NEXT: slli a0, a0, 3
; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -136,8 +136,8 @@ define i32 @addmul12(i32 %a, i32 %b) {
; RV32I-LABEL: addmul12:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: slli a0, a0, 3
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -193,8 +193,8 @@ define i32 @addmul24(i32 %a, i32 %b) {
; RV32I-LABEL: addmul24:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 3
; RV32I-NEXT: slli a0, a0, 5
; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -269,8 +269,8 @@ define i32 @mul96(i32 %a) {
; RV32I-LABEL: mul96:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 5
; RV32I-NEXT: slli a0, a0, 7
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: slli a0, a0, 6
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32XTHEADBA-LABEL: mul96:
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/rv32zba.ll
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Expand Up @@ -85,8 +85,8 @@ define i32 @addmul6(i32 %a, i32 %b) {
; RV32I-LABEL: addmul6:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 1
; RV32I-NEXT: slli a0, a0, 3
; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -135,8 +135,8 @@ define i32 @addmul12(i32 %a, i32 %b) {
; RV32I-LABEL: addmul12:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: slli a0, a0, 3
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -210,8 +210,8 @@ define i32 @addmul24(i32 %a, i32 %b) {
; RV32I-LABEL: addmul24:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 3
; RV32I-NEXT: slli a0, a0, 5
; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -310,8 +310,8 @@ define i32 @mul96(i32 %a) {
; RV32I-LABEL: mul96:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 5
; RV32I-NEXT: slli a0, a0, 7
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: slli a0, a0, 6
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32ZBA-LABEL: mul96:
Expand Down Expand Up @@ -1272,8 +1272,8 @@ define ptr @shl_add_knownbits(ptr %p, i32 %i) {
; RV32I-NEXT: slli a1, a1, 18
; RV32I-NEXT: srli a1, a1, 18
; RV32I-NEXT: slli a2, a1, 1
; RV32I-NEXT: slli a1, a1, 3
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: srli a1, a1, 3
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/rv64xtheadba.ll
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Expand Up @@ -94,8 +94,8 @@ define i64 @addmul6(i64 %a, i64 %b) {
; RV64I-LABEL: addmul6:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a0, 1
; RV64I-NEXT: slli a0, a0, 3
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -113,8 +113,8 @@ define i64 @disjointormul6(i64 %a, i64 %b) {
; RV64I-LABEL: disjointormul6:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a0, 1
; RV64I-NEXT: slli a0, a0, 3
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
Expand Down Expand Up @@ -151,8 +151,8 @@ define i64 @addmul12(i64 %a, i64 %b) {
; RV64I-LABEL: addmul12:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a0, 2
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: slli a0, a0, 3
; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
Expand Down Expand Up @@ -227,8 +227,8 @@ define i64 @addmul24(i64 %a, i64 %b) {
; RV64I-LABEL: addmul24:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a0, 3
; RV64I-NEXT: slli a0, a0, 5
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
Expand Down Expand Up @@ -527,8 +527,8 @@ define i64 @mul96(i64 %a) {
; RV64I-LABEL: mul96:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 5
; RV64I-NEXT: slli a0, a0, 7
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: slli a0, a0, 6
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64XTHEADBA-LABEL: mul96:
Expand Down Expand Up @@ -990,8 +990,8 @@ define signext i32 @mulw192(i32 signext %a) {
; RV64I-LABEL: mulw192:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 6
; RV64I-NEXT: slli a0, a0, 8
; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 7
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64XTHEADBA-LABEL: mulw192:
Expand Down
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