[SelectionDAG][WIP] Move HwMode expansion from tablegen to SelectionISel. #174471

topperc · 2026-01-05T20:00:37Z

The way HwMode is currently implemented, tablegen duplicates each
pattern that is dependent on hardware mode. The HwMode predicate is
added as a pattern predicate on the duplicated pattern.

RISC-V uses HwMode on the GPR register class which means almost every
isel pattern is affected by HwMode. This results in the isel table
being nearly twice the size it would be if we only had a single GPR size.

This patch proposes to do the expansion at instruction selection time
instead. To accomplish this new opcodes like OPC_CheckTypeByHwMode
are added to the isel table. The unique combinations of types and HwMode
are converted to an index that is the payload for the new opcodes.
TableGen emits a new virtual function getValueTypeByHwMode that uses
this index and the current HwMode to look up the type.

This reduces the size of the isel table on RISC-V from ~2.38 million bytes
to ~1.38 million bytes.

I did not add an OPC_SwitchTypeByHwMode opcode yet. If the VT requires a
hardware mode, we emit an OPC_Scope+OPC_CheckTypeByHwMode instead. I
expect adding an OPC_SwitchTypeByHwMode could further reduce the table
size. I will investigate this as a follow up.

I haven't measured yet, but it's possible the new getValueTypeByHwMode
may have an affect on compile time. If necessary we could add a cache on
this lookup to mitigate some impact.

Many of the matcher classes in tablegen now use ValueTypeByHwMode instead
of MVT. This may have an impact on the memory usage and runtime of tablegen.
We can mitigate some of this by splitting the matchers into MVT and
ValueTypeByHwMode versions. We can also explore alternate data structures
for ValueTypeByHwMode instead of a std::map. Maybe a sorted vector.

I plan to do some cleanup to try to reduce some code duplication, but
I wanted to get early feedback on the direction.

Given the scope of this patch and the timing of the LLVM 22 branch,
I don't expect to commit this until after the branch.

A similar change can be made to GlobalISel as a follow up.

…Sel. The way HwMode is currently implemented, tablegen duplicates each pattern that is dependent on hardware mode. The HwMode predicate is added as a pattern predicate on the duplicated pattern. RISC-V uses HwMode on the GPR register class which means almost every isel pattern is affected by HwMode. This results in the isel table being nearly twice the size it would be if we only had a single GPR size. This patch proposes to do the expansion at instruction selection time instead. To accomplish this new opcodes like OPC_CheckTypeByHwMode are added to the isel table. The unique combinations of types and HwMode are converted to an index that is the payload for the new opcodes. TableGen emits a new virtual function getValueTypeByHwMode that uses this index and the current HwMode to look up the type. This reduces the size of the isel table on RISC-V from ~2.38 million bytes to ~1.38 million bytes. I did not add an OPC_SwitchTypeByHwMode opcode yet. If the VT requires a hardware mode, we emit an OPC_Scope+OPC_CheckTypeByHwMode instead. I expect adding an OPC_SwitchTypeByHwMode could further reduce the table size. I will investigate this as a follow up. I haven't measured yet, but it's possible the new getValueTypeByHwMode may have an affect on compile time. If necessary we could add a cache on this lookup to mitigate some impact. Many of the matcher classes in tablegen now use ValueTypeByHwMode instead of MVT. This may have an impact on the memory usage and runtime of tablegen. We can mitigate some of this by splitting the matchers into MVT and ValueTypeByHwMode versions. We can also explore alternate data structures for ValueTypeByHwMode instead of a std::map. Maybe a sorted vector. I plan to do some cleanup to try to reduce some code duplication, but I wanted to get early feedback on the direction. Given the scope of this patch and the timing of the LLVM 22 branch, I don't expect to commit this until after the branch.

llvmbot · 2026-01-05T20:01:08Z

@llvm/pr-subscribers-llvm-selectiondag

@llvm/pr-subscribers-tablegen

Author: Craig Topper (topperc)

Changes