[RISC-V][Mach-O] Print immediate operands in hexadecimal format.

[fpetrogalli]

This is done for logical operations and auipc/lui.

Patch based on code written by Tim Northover.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Francesco Petrogalli (fpetrogalli)

Changes

This is done for logical operations and auipc/lui.

Patch based on code written by Tim Northover.

It is based on the PR at #141682

---

Full diff: https://github.com/llvm/llvm-project/pull/174505.diff

3 Files Affected:

• (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp (+28)
• (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h (+2)
• (added) llvm/test/MC/RISCV/hex-imm-macho.s (+16)

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index f2c5f6947aa00..7dc3ed90e683a 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -95,6 +95,11 @@ void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
     return;
   }
 
+  if (MO.isImm() && STI.getTargetTriple().isOSBinFormatMachO()) {
+    printImm(MI, OpNo, STI, O);
+    return;
+  }
+
   if (MO.isImm()) {
     markup(O, Markup::Immediate) << formatImm(MO.getImm());
     return;
@@ -337,6 +342,29 @@ void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
   O << ".t";
 }
 
+void RISCVInstPrinter::printImm(const MCInst *MI, unsigned OpNo,
+                                const MCSubtargetInfo &STI, raw_ostream &O) {
+  const MCOperand &Op = MI->getOperand(OpNo);
+
+  switch (MI->getOpcode()) {
+  case RISCV::ANDI:
+  case RISCV::ORI:
+  case RISCV::XORI:
+  case RISCV::C_ANDI:
+  case RISCV::AUIPC:
+  case RISCV::LUI:
+    break;
+  default:
+    O << Op.getImm();
+    return;
+  }
+
+  uint64_t Imm = Op.getImm();
+  if (!STI.hasFeature(RISCV::Feature64Bit))
+    Imm = static_cast<uint32_t>(Imm);
+  O << format("%#llx", Imm);
+}
+
 const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) {
   // When PrintAliases is enabled, and EmitX8AsFP is enabled, x8 will be printed
   // as fp instead of s0. Note that these similar registers are not replaced:
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
index f8b8fd34abbb4..17469bd87e34e 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
@@ -52,6 +52,8 @@ class RISCVInstPrinter : public MCInstPrinter {
                        const MCSubtargetInfo &STI, raw_ostream &O);
   void printVMaskReg(const MCInst *MI, unsigned OpNo,
                      const MCSubtargetInfo &STI, raw_ostream &O);
+  void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+                raw_ostream &O);
   void printRegList(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);
   void printStackAdj(const MCInst *MI, unsigned OpNo,
diff --git a/llvm/test/MC/RISCV/hex-imm-macho.s b/llvm/test/MC/RISCV/hex-imm-macho.s
new file mode 100644
index 0000000000000..5344bf2a41858
--- /dev/null
+++ b/llvm/test/MC/RISCV/hex-imm-macho.s
@@ -0,0 +1,16 @@
+// RUN: llvm-mc -triple riscv32-apple-unknown-macho -mattr=+c --riscv-no-aliases %s | FileCheck %s
+
+// CHECK: andi a0, a0, 0x190
+// CHECK: ori a0, a0, 0x400
+// CHECK: xori a0, a0, 0xfffffff4
+andi a0, a0, 400
+ori a0, a0, 1024
+xori a0, a0, -12
+
+// CHECK: c.andi s0, 0x1f
+c.andi s0, 31
+
+// CHECK: auipc a0, 0x3e8
+// CHECK: lui a0, 0x2710
+auipc a0, 1000
+lui a0, 10000

[github-actions]

🪟 Windows x64 Test Results

• 129183 tests passed
• 2844 tests skipped

✅ The build succeeded and all tests passed.

[fpetrogalli]

🪟 Windows x64 Test Results

• 129167 tests passed
• 2843 tests skipped

✅ The build succeeded and all tests passed.

Yuppie! :)

[lenary]

LGTM

[topperc]

LGTM

[topperc]

LGTM