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[pwm,rtl] Rewrite two write-enables more explicitly #25062

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@rswarbrick rswarbrick commented Nov 8, 2024

This is actually two commits, which both behave essentially the same (with similar notes). The commit message for the first is:

The behaviour will be the same, but it avoids an expression coverage hole being reported for blink_en_i == 0 and blink_ctr_q == 1. This can't actually happen: blink_ctr_q can only be updated by being set to blink_ctr_d (on this line). If blink_en_i is false then blink_ctr_d == 0.

The only other way to reach the item would be to have incremented blink_ctr_q and then disabled blink. But disabling blink needs a register write, which will set a bit in clr_blink_cntr in pwm_core, which means that clr_blink_cntr_i is true, zeroing blink_ctr_q.

Coding this write-enable more explicitly gets rid of the expression coverage item.

@rswarbrick rswarbrick changed the title [pwm,rtl] Rewrite a write-enable more explicitly [pwm,rtl] Rewrite two write-enables more explicitly Nov 8, 2024
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This looks good, thanks @rswarbrick !

But can you please combine the two commits? Both commits touch the very same file and they both implement a very similar change without functional impact. I don't think we would ever want to undo only one of them.

The behaviour will be the same, but the first change avoids an
expression coverage hole being reported for `blink_en_i == 0` and
`blink_ctr_q == 1`. This can't actually happen: `blink_ctr_q` can only
be updated by being set to `blink_ctr_d` (on this line). If
`blink_en_i` is false then `blink_ctr_d == 0`.

The only other way to reach the item would be to have incremented
`blink_ctr_q` and then disabled blink. But disabling blink needs a
register write, which will set a bit in `clr_blink_cntr` in
`pwm_core`, which means that `clr_blink_cntr_i` is true, zeroing
`blink_ctr_q`.

Coding this write-enable more explicitly gets rid of the expression
coverage item.

The second change covers two further coverage holes, that have
htbt_ctr_q and the write predicate false (either because blink_en_i is
false or htbt_en_i is false).

As before, this isn't possible. If the predicate is not true then
htbt_ctr_d will be zero (so htbt_ctr_q cannot become nonzero). If it
was nonzero before and we are changing the predicate to become false,
the register write will cause clr_blink_cntr_i to go high, zeroing
htbt_ctr_q.

Signed-off-by: Rupert Swarbrick <[email protected]>
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Good point: done. Would you mind doing the "unauthorized changes dance"?

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CHANGE AUTHORIZED: hw/ip/pwm/rtl/pwm_chan.sv

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