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@oscc-ip

OSCC IP Project

Develop and maintain IP Projects under ECOS Team

OSCC IP: A series of Verified HDL IP with Accurate-cycle and Event-driven Model

Hi, OSCC IP Project 👋

OSCC IP Project contains a bundle of IPs which aim to improve development experience of processor and SoC design. Now it mainly focus on frontend and verification field. We hope it can be integrated by other components to build a common workflow for agile hardware development from frontend to backend one day.

Motivation

Template

Refer to the template repo. If you want to create a new ip repo, You need to:

  • Use this repository template to create a new repo
  • Update the content [IP NAME] in header file and remove the header file.

Style

refer to the style.md.

Contribution

If you want to contribute to this project, be sure to review the guidelines. This is an open project and contributions and collaborations are always welcome!! This project adheres to OSCC IP's code_of_conduct. By participating, you are expected to uphold this code.

we use GitHub issues for tracking requests and bugs, so please direct specific questions to issues panel.

The OSCC IP project strives to abide by generally accepted best practices in open-source software development, you can issue bugs, pull requests, new features and modification suggestions freely. Your feedbacks could help us ensure a bright future for this project. We value and treasure every issue or contribution, big or small. 😄

License

All of the IPs codes are redistributed or released under the OSI Approved LICENSE MulanPSL2.

Acknowledgement

Reference

Pinned Loading

  1. sdram sdram Public

    An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

    Scala 16 2

Repositories

Showing 6 of 6 repositories
  • .github Public
    oscc-ip/.github’s past year of commit activity
    1 GPL-3.0 0 0 0 Updated Apr 20, 2025
  • artifact Public

    A repository provides build artifacts for various open-source EDA tools.

    oscc-ip/artifact’s past year of commit activity
    0 0 0 0 Updated Apr 18, 2025
  • sdram Public

    An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

    oscc-ip/sdram’s past year of commit activity
    Scala 16 2 0 1 Updated Mar 29, 2025
  • nangate Public

    Nangate Open Cell Library

    oscc-ip/nangate’s past year of commit activity
    Verilog 2 Apache-2.0 0 0 0 Updated Jan 28, 2025
  • cl2-chisel Public
    oscc-ip/cl2-chisel’s past year of commit activity
    Scala 1 0 0 0 Updated Jan 8, 2025
  • cl2 Public
    oscc-ip/cl2’s past year of commit activity
    SystemVerilog 1 MulanPSL-2.0 0 0 0 Updated Jan 8, 2025

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