Rename all instances of riscv-pac to riscv-types besides docs

Cargo.toml

@@ -2,7 +2,7 @@
 resolver = "2"
 members = [
     "riscv",
-    "riscv-pac",
+    "riscv-types",
     "riscv-peripheral",
     "riscv-rt",
     "riscv-semihosting",
@@ -13,7 +13,7 @@ members = [
 
 default-members = [
     "riscv",
-    "riscv-pac",
+    "riscv-types",
     "riscv-peripheral",
     "riscv-rt",
     "riscv-semihosting",

riscv-peripheral/Cargo.toml

@@ -17,7 +17,7 @@ license = "ISC"
 embedded-hal = "1.0.0"
 paste = "1.0"
 riscv = { path = "../riscv", version = "0.15.0" }
-riscv-pac = { path = "../riscv-pac", version = "0.2.0" }
+riscv-types = { path = "../riscv-types", version = "0.2.0" }
 
 [package.metadata.docs.rs]
 all-features = true

riscv-peripheral/src/aclint.rs

@@ -7,7 +7,7 @@ pub mod mswi;
 pub mod mtimer;
 pub mod sswi;
 
-pub use riscv_pac::HartIdNumber; // re-export useful riscv-pac traits
+pub use riscv_types::HartIdNumber; // re-export useful riscv-types traits
 
 /// Trait for a CLINT peripheral.
 ///

riscv-peripheral/src/lib.rs

@@ -3,7 +3,7 @@
 #![deny(missing_docs)]
 #![no_std]
 
-pub use riscv_pac::result; // re-export the result module
+pub use riscv_types::result; // re-export the result module
 
 pub mod common; // common definitions for all peripherals
 pub mod hal; // trait implementations for embedded-hal

riscv-peripheral/src/macros.rs

@@ -31,7 +31,7 @@ pub use paste::paste;
 /// ## Base address and per-HART mtimecmp registers, private `fn new()` function
 ///
 /// ```
-/// use riscv_pac::result::{Error, Result};
+/// use riscv_types::result::{Error, Result};
 ///
 /// /// HART IDs for the target CLINT peripheral
 /// #[derive(Clone, Copy, Debug, Eq, PartialEq)]
@@ -142,7 +142,7 @@ macro_rules! clint_codegen {
 /// ## Base address and per-HART context proxies, private `fn new()` function
 ///
 /// ```
-/// use riscv_pac::result::{Error, Result};
+/// use riscv_types::result::{Error, Result};
 ///
 /// /// HART IDs for the target CLINT peripheral
 /// #[derive(Clone, Copy, Debug, Eq, PartialEq)]

riscv-peripheral/src/plic.rs

@@ -8,8 +8,8 @@ pub mod pendings;
 pub mod priorities;
 pub mod threshold;
 
-// re-export useful riscv-pac traits
-pub use riscv_pac::{HartIdNumber, InterruptNumber, PriorityNumber};
+// re-export useful riscv-types traits
+pub use riscv_types::{HartIdNumber, InterruptNumber, PriorityNumber};
 
 use riscv::register::{mhartid, mie, mip};
 
@@ -200,7 +200,7 @@ impl<P: Plic> CTX<P> {
 #[cfg(test)]
 pub(crate) mod test {
     use crate::test::HartId;
-    use riscv_pac::HartIdNumber;
+    use riscv_types::HartIdNumber;
 
     #[allow(dead_code)]
     #[test]

riscv-peripheral/src/plic/claim.rs

@@ -1,7 +1,7 @@
 //! Interrupt claim/complete register
 
 use crate::common::unsafe_peripheral;
-use riscv_pac::ExternalInterruptNumber;
+use riscv_types::ExternalInterruptNumber;
 
 unsafe_peripheral!(CLAIM, u32, RW);
 
@@ -32,7 +32,7 @@ impl CLAIM {
 mod test {
     use super::*;
     use crate::test::Interrupt;
-    use riscv_pac::InterruptNumber;
+    use riscv_types::InterruptNumber;
 
     #[test]
     fn test_claim() {

riscv-peripheral/src/plic/enables.rs

@@ -1,7 +1,7 @@
 //! Interrupt enables register of a PLIC context.
 
 use crate::common::{Reg, RW};
-use riscv_pac::ExternalInterruptNumber;
+use riscv_types::ExternalInterruptNumber;
 
 /// Enables register of a PLIC context.
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]

riscv-peripheral/src/plic/pendings.rs

@@ -1,7 +1,7 @@
 //! Interrupt pending bits register.
 
 use crate::common::{Reg, RO};
-use riscv_pac::ExternalInterruptNumber;
+use riscv_types::ExternalInterruptNumber;
 
 /// Interrupts pending bits register.
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]

riscv-peripheral/src/plic/priorities.rs

@@ -1,7 +1,7 @@
 //! Interrupts Priorities register.
 
 use crate::common::{Reg, RW};
-use riscv_pac::{ExternalInterruptNumber, PriorityNumber};
+use riscv_types::{ExternalInterruptNumber, PriorityNumber};
 
 /// Interrupts priorities register.
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
@@ -71,7 +71,7 @@ impl PRIORITIES {
 mod test {
     use super::*;
     use crate::test::{Interrupt, Priority};
-    use riscv_pac::InterruptNumber;
+    use riscv_types::InterruptNumber;
 
     #[test]
     fn test_priorities() {

riscv-rt/CHANGELOG.md

@@ -7,10 +7,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
-### Changed
-
-- Adapted to new `riscv` version.
-
 ## [v0.16.0] - 2025-09-08
 
 ### Added

riscv-rt/Cargo.toml

@@ -24,8 +24,8 @@ targets = [
 riscv-target-parser = { path = "../riscv-target-parser", version = "0.1.2" }
 
 [dependencies]
-riscv = { path = "../riscv", version = "0.15.0", features = ["rt"] }
-riscv-pac = { path = "../riscv-pac", version = "0.2.0" }
+riscv = { path = "../riscv", version = "0.15.0" }
+riscv-types = { path = "../riscv-types", version = "0.2.0" }
 riscv-rt-macros = { path = "macros", version = "0.6.0" }
 
 defmt = { version = "1.0.1", optional = true }
@@ -38,7 +38,7 @@ pre-init = []
 post-init = []
 s-mode = ["riscv-rt-macros/s-mode"]
 single-hart = []
-v-trap = ["riscv-rt-macros/v-trap", "riscv/rt-v-trap"]
+v-trap = ["riscv-rt-macros/v-trap"]
 u-boot = ["riscv-rt-macros/u-boot", "single-hart"]
 no-interrupts = []
 no-exceptions = []

riscv-rt/src/interrupts.rs

@@ -17,10 +17,10 @@
 //! you may need to opt out this module. To do so, activate the `no-interrupts` feature of the
 //! `riscv-rt` crate.
 
+// In vectored mode, we also must provide a vector table
 #[riscv::pac_enum(unsafe CoreInterruptNumber)]
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[allow(dead_code)] // otherwise compiler complains about Interrupt not being used
 enum Interrupt {
     SupervisorSoft = 1,
     MachineSoft = 3,

riscv-rt/src/lib.rs

@@ -662,8 +662,8 @@ use riscv::register::{
     mtvec::{self as xtvec, Mtvec as Xtvec, TrapMode},
 };
 
-pub use riscv_pac::*;
 pub use riscv_rt_macros::{core_interrupt, entry, exception, external_interrupt};
+pub use riscv_types::*;
 
 #[cfg(feature = "post-init")]
 pub use riscv_rt_macros::post_init;

riscv-pac/CHANGELOG.md → riscv-types/CHANGELOG.md

@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+- Rename all instances of `riscv-pac` with `riscv-types`
+
 ## [v0.2.0] - 2024-10-19
 
 ### Added

riscv-pac/Cargo.toml → riscv-types/Cargo.toml

@@ -1,13 +1,13 @@
 [package]
-name = "riscv-pac"
+name = "riscv-types"
 version = "0.2.0"
 edition = "2021"
 rust-version = "1.60"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <[email protected]>"]
 categories = ["embedded", "hardware-support", "no-std"]
 description = "Low level access to RISC-V processors"
-documentation = "https://docs.rs/riscv-pac"
+documentation = "https://docs.rs/riscv-types"
 keywords = ["riscv", "register", "peripheral"]
 license = "ISC"
 

riscv/CHANGELOG.md

@@ -12,11 +12,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Added DCSR (Debug Control and Status Register) CSR support for the RISC-V
 - Add `miselect` CSR
 - Improved assembly macro handling in asm.rs
-- New `rt` and `rt-v-trap` features to opt-in `riscv-rt`-related code in `riscv::pac_enum` macro.
-
-# Changed
-
-- Now, `riscv::pac_enum` macro only includes trap-related code if `rt` or `rt-v-trap` features are enabled.
 
 ## [v0.15.0] - 2025-09-08
 

riscv/Cargo.toml

@@ -23,12 +23,10 @@ targets = [
 default = ["riscv-macros"]
 s-mode = []
 critical-section-single-hart = ["critical-section/restore-state-bool"]
-rt = ["riscv-macros/rt"]
-rt-v-trap = ["rt", "riscv-macros/rt-v-trap"]
 
 [dependencies]
 critical-section = "1.2.0"
 embedded-hal = "1.0.0"
-riscv-pac = { path = "../riscv-pac", version = "0.2.0" }
+riscv-types = { path = "../riscv-types", version = "0.2.0" }
 riscv-macros = { path = "macros", version = "0.3.0", optional = true }
 paste = "1.0.15"

riscv/macros/Cargo.toml

@@ -15,10 +15,6 @@ edition = "2021"
 [lib]
 proc-macro = true
 
-[features]
-rt = []
-rt-v-trap = ["rt"]
-
 [dependencies]
 proc-macro2 = "1.0"
 quote = "1.0"