-
Notifications
You must be signed in to change notification settings - Fork 186
riscv: add the mvien + mvienh CSR
#361
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
base: master
Are you sure you want to change the base?
Conversation
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
What do you think about returning results to notify users about potential issues with their interrupt enum?
I think this is a good idea. Do you think we should also provide an example pub struct VirtualInterrupt {
SupervisorSoftware = 1,
SupervisorTimer = 5,
SupervisorExternal = 9,
Interrupt(RangedUsize<13, 63>),
}
/// SAFETY: `Interrupt` represents the virtual RISC-V interrupts
unsafe impl InterruptNumber for VirtualInterrupt {
const MAX_INTERRUPT_NUMBER: usize = Mvien::MAX_INTERRUPT;
#[inline]
fn number(self) -> usize {
match self {
Self::SupervisorSoftware => 1,
Self::SupervisorTimer => 5,
Self::SupervisorExternal => 9,
Self::Interrupt(int) => int.inner(),
}
}
#[inline]
fn from_number(value: usize) -> Result<Self> {
match value {
1 => Ok(Self::SupervisorSoftware),
5 => Ok(Self::SupervisorTimer),
9 => Ok(Self::SupervisorExternal),
_ => RangedUsize::try_from(value).map(Self::Interrupt),
}
}
}Maybe this is better left to higher-level libraries? |
We have this one: https://github.com/rust-embedded/riscv/blob/master/riscv/src/interrupt/supervisor.rs There is another for machine mode. |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Let me know what you think. If you agree with my comments, apply the change and let's merge it!
Awesome! I applied the changes. Let me squash down all of the fixup commits. |
Adds the `mvien` + `mvienh` CSR to represent the `Machine Virtual Interrupt Enable` registers. Authored-by: Elle Rhumsaa <[email protected]> Co-authored-by: Román Cárdenas Rodríguez <[email protected]>
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
LGTM
Adds the
mvien+mvienhCSR to represent theMachine Virtual Interrupt Enableregisters.Related: #1, #226