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@0xllx0 0xllx0 commented Oct 31, 2025

Adds the mvien + mvienh CSR to represent the Machine Virtual Interrupt Enable registers.

Related: #1, #226

@0xllx0 0xllx0 requested a review from a team as a code owner October 31, 2025 12:56
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What do you think about returning results to notify users about potential issues with their interrupt enum?

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0xllx0 commented Nov 5, 2025

What do you think about returning results to notify users about potential issues with their interrupt enum?

I think this is a good idea. Do you think we should also provide an example VirtualInterrupt enum, something like:

pub struct VirtualInterrupt {
    SupervisorSoftware = 1,
    SupervisorTimer = 5,
    SupervisorExternal = 9,
    Interrupt(RangedUsize<13, 63>),
}

/// SAFETY: `Interrupt` represents the virtual RISC-V interrupts
unsafe impl InterruptNumber for VirtualInterrupt {
    const MAX_INTERRUPT_NUMBER: usize = Mvien::MAX_INTERRUPT;

    #[inline]
    fn number(self) -> usize {
        match self {
            Self::SupervisorSoftware => 1,
            Self::SupervisorTimer => 5,
            Self::SupervisorExternal => 9,
            Self::Interrupt(int) => int.inner(),
        }
    }

    #[inline]
    fn from_number(value: usize) -> Result<Self> {
        match value {
            1 => Ok(Self::SupervisorSoftware),
            5 => Ok(Self::SupervisorTimer),
            9 => Ok(Self::SupervisorExternal),
            _ => RangedUsize::try_from(value).map(Self::Interrupt),
        }
    }
}

Maybe this is better left to higher-level libraries?

@romancardenas
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What do you think about returning results to notify users about potential issues with their interrupt enum?

I think this is a good idea. Do you think we should also provide an example VirtualInterrupt enum, something like:

We have this one: https://github.com/rust-embedded/riscv/blob/master/riscv/src/interrupt/supervisor.rs

There is another for machine mode.

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Let me know what you think. If you agree with my comments, apply the change and let's merge it!

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0xllx0 commented Nov 5, 2025

Let me know what you think. If you agree with my comments, apply the change and let's merge it!

Awesome! I applied the changes. Let me squash down all of the fixup commits.

Adds the `mvien` + `mvienh` CSR to represent the `Machine Virtual
Interrupt Enable` registers.

Authored-by: Elle Rhumsaa <[email protected]>
Co-authored-by: Román Cárdenas Rodríguez <[email protected]>
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LGTM

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