Review Request: Rough Implementation of LBR on Memtrace - #8

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takhandipu wants to merge 111 commits into

stanford-mast:memtracefrom

takhandipu:memtrace

Commits on Dec 24, 2019

clang zero latency icache consumes 85% less cycles
takhandipu
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6f281b5
LBR data is defined, but mechanism is not
takhandipu
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3a5e8e0
Implemented LBR
Tanvir Ahmed Khan
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d97aa92
Semantic bug fix
Tanvir Ahmed Khan
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0db17e3
Checking whether we can pass LBR pointer via MemReq
Tanvir Ahmed Khan
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3ce9dfb
LBR uses uint64_t instead of Address to ensure MemReq can use that
Tanvir Ahmed Khan
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3690a2d
remove bits/stdc++.h from lbr.h
Tanvir Ahmed Khan
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e002c68
Trying to fix MemReq plain old data type error
Tanvir Ahmed Khan
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c2130ac

Commits on Dec 25, 2019

Trying to see whether ooo_filter_cache load can take lbr (by feault nullptr)
Tanvir Ahmed Khan
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ef7f0fd
Trying to see whether filter_cache load can take lbr (by feault nullptr)
Tanvir Ahmed Khan
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4d8b751
Trying to see whether filter_cache replace and cache_arrays lookup can take lbr (by feault nullptr)
Tanvir Ahmed Khan
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1996ccf
LBR logging for a cache_arrays miss is enabled
Tanvir Ahmed Khan
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2e9c002
Tiny syntactic bug fiz
Tanvir Ahmed Khan
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bebf08d
Enabling lbr logging for each L1i->load() misses
Tanvir Ahmed Khan
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0917048
Minor semantic bug fiz
Tanvir Ahmed Khan
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b932c7a
Minor implementation bug fix
Tanvir Ahmed Khan
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6aabb32
l1i->load for ooo_core now includes program counter so that we can log miss
Tanvir Ahmed Khan
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5b52963
Wrong path L1i fetch does not include LBR or PC logging, Have to talk with Professor Litz regarding that
Tanvir Ahmed Khan
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2c5689b
LBR data for a given BBL is pushed even before calling ooo_core->bbl on it, again have to check with Professor Litz
Tanvir Ahmed Khan
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a77cec4
added missed cache line address when logging LBR, I guess LBR implementation is complete
Tanvir Ahmed Khan
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e6be05b
forgot to add lbr.h in the previous commit, I guess LBR implementation is complete
Tanvir Ahmed Khan
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fbd76e1

Commits on Jan 8, 2020

LBR driven prefetch distance based prefetching implementation on zsim is complete
takhandipu
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f7634af
Syntax error fix
takhandipu
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bd5aab4
Syntax error fix
takhandipu
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50829ab
Syntax error fix
takhandipu
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bb80432
Syntax error fix
takhandipu
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b500b9d
Syntax error fix
takhandipu
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39bed0b
Trying to fix c++ map SIGFPE
takhandipu
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11ad32c
Trying to fix c++ map SIGFPE
takhandipu
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fe83948

Commits on Jan 9, 2020

Commits on Jan 10, 2020

Major bug fix regarding front-end cycle computation on prefetched instructions
takhandipu
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8b3256c

Commits on Jan 20, 2020

Initiated the prefetch priority reduction in replacement policy
takhandipu
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10b7368
Didn't work, undoing last commit, :-(
takhandipu
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b97795f
Prefetches don't update replacement policy timestamp
takhandipu
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56cd56d
Previous one segfaulted, let's see whether this one works
takhandipu
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47011d0
Picking the third one worsen the performance
takhandipu
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c940ffc
Picking the third one worsen the performance
takhandipu
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185c8b0
Now picking the third one from the reverse order
takhandipu
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51b6654
Now picking the median
takhandipu
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2e97283

Commits on Jan 21, 2020

second latest one works best empirically, so we picked the second last replacement timestamp
takhandipu
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e20f6b5

Commits on Jan 22, 2020

Added new bbl-info printing capability to log number of instructions in the bbl and the size of the bbl
takhandipu
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184b270

Commits on Jan 23, 2020

Trying pushing on to lbr after the bbl function
takhandipu
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e8a5683
Undoing previous commit
takhandipu
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d879b9c

Commits on Jan 24, 2020

Added cfg flags to enable/disable first-pass profile data and prefetch having lower priority on replacement policy than demand-load
takhandipu
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ae92a07

Commits on Jan 28, 2020

Fixed bug in zeroLatencyCache implementation, ideal cache now has access latency
takhandipu
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8ea842b

Commits on Jan 29, 2020

Started merging PT trace reader in to the memtrace branch
takhandipu
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386ea17
Not yet compiled
takhandipu
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529e41f
Added dummy implementation of trace_reader virtual functions for pt trace reader
takhandipu
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9c3f196
Debugging why xed decoding is failing
takhandipu
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c165df3
Bug fix while calling fill cache from pt trace reader
takhandipu
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97b6ee0
Making pt instruction valid, but mem ops are still invalid
takhandipu
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d2f6391
Making memory ops valid, but memory addresses are still invalid
takhandipu
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581f6d4

Commits on Jan 30, 2020

Implemented the static code bloat fetch impact on the trace and the simulation
takhandipu
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e3a3053

Commits on Feb 10, 2020

Prefetch buffer implementation is complete but may not work for cRec conflict
takhandipu
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fe104ee

Commits on Feb 11, 2020

Minor compile fix
takhandipu
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ed3671b
Minor compile fix
takhandipu
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dba5e4b
Minor compile fix
takhandipu
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097d34a
name convention change in dynamorio, due to commit 5ed1a118e820fccae7e75d85525cb7d5dbde6d2a
takhandipu
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cf19392
Minor update
takhandipu
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f65a866
Removing load store match between expected and actual so that PT trace-driven simulation does not fail in some cases
takhandipu
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03e007b

Commits on Feb 14, 2020

Adding changes for prefetch buffer and hacky solution of jitted code bbl cache error
Tanvir Ahmed Khan
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9755424
moving prefetch buffer from filter cache to ooo filter cache to avoid cRec error
takhandipu
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562dd93
Minor compile fix
takhandipu
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76c6a92
Minor compile fix
takhandipu
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eda75c9
Minor bug fix
takhandipu
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38a979c
Minor bug fix
takhandipu
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b177791

Commits on Feb 15, 2020

Removed BBL decoding cache for PT trace and added bbl info trace for self modifying code
takhandipu
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3a896cf
Minor compile fix
takhandipu
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72dcd6b
Minor compile fix
takhandipu
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0cb2ee6
Enabling the disabled assertion after PT decoding cache disable
takhandipu
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9be9e66
Minor bug fix
takhandipu
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21719cc
Minor bug fix
takhandipu
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df85483
Minor update
takhandipu
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f478bd5

Commits on Feb 26, 2020

Implemented context sensitive improvement on zsim
takhandipu
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2794794
Minor compile fix
takhandipu
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438bd8c

Commits on Feb 27, 2020

Bug fix
takhandipu
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02bd99b
Added speculative flag on software prefetch so that mGETS does not increase for missed prefetch
takhandipu
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fd70b1b

Commits on Feb 28, 2020

Commits on Mar 2, 2020

L1i prefetch now uses issuePrefetch
takhandipu
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bdd030a
making isSW flag true for software prefetch
takhandipu
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9a5773a
Making prefetches skip 1 to see what is the resut
takhandipu
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0e52c52
Undoing previous commit which reduces the performance by 14%
takhandipu
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9b28dea
Defining MONITOR_MISS_PCS based on Heiner's suggestion
takhandipu
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fae80ae
monitoring top-25 missed PCs
takhandipu
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95b7828

Commits on Mar 3, 2020

Adding a new counter profPrefLateSavedCycles
takhandipu
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21e8f8e

Commits on Mar 20, 2020

Modified context-sensitive prefetch to support variable sized context
Tanvir Ahmed Khan
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77baa28
context size up to 8
Tanvir Ahmed Khan
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a5593a3
Minor fix
Tanvir Ahmed Khan
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1f85e8c

Commits on Mar 27, 2020

made isSW prefetch false to see the results of all different counters
Tanvir Ahmed Khan
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45e7ceb

Commits on Mar 29, 2020

divided profPrefEarlyMiss counter into profPrefEarlyMiss and profPrefNeverUsed counters based on 400 cycle difference from req->cycle and candidate's startCycle
Tanvir Ahmed Khan
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67b6298

Commits on Apr 1, 2020

Added a new entry at the end of the LBR string to map it on to the dcfg
Tanvir Ahmed Khan
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1a5f6cc
minor bug fix
Tanvir Ahmed Khan
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a004e37

Commits on Apr 3, 2020

Changed context sensitive prefetch file description again
Tanvir Ahmed Khan
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5991382
minor bug fix context sensitive prefetch
Tanvir Ahmed Khan
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febc4d4
minor garbage collection
Tanvir Ahmed Khan
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412a8c1

Commits on Apr 9, 2020

AsmDB n-next line prefetching sim parameter is added to simulate the analysis
Tanvir Ahmed Khan
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9a45a0c
AsmDB miss-based next line prefetching is implemented, let's see whether it runs or not
Tanvir Ahmed Khan
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ed7862e

Commits on Apr 13, 2020

Figuring out verilator next line anomaly
Tanvir Ahmed Khan
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04b7242

Commits on Apr 14, 2020

Trying to combine context and coalesce in a better way
Tanvir Ahmed Khan
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eec8b6c

Commits on Apr 18, 2020

Added the false positive rate parameter on the context sensitive prefetch
Tanvir Ahmed Khan
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fd7fc0d

Commits on Feb 11, 2021

Replace repz's with nops
takhandipu
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6d222ca
repz's could be 4 bytes as well
takhandipu
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bd1b17b

Commits on Feb 18, 2021