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[IRGen] Use at least Int8 for extra tag bits #81151

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May 1, 2025
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[IRGen] Use at least Int8 for extra tag bits #81151

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32 changes: 10 additions & 22 deletions lib/IRGen/GenEnum.cpp
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Expand Up @@ -1430,10 +1430,7 @@ namespace {
// types other than i1 or power-of-two-byte sizes like i8, i16, etc. inhibit
// FastISel and expose backend bugs.
static unsigned getIntegerBitSizeForTag(unsigned tagBits) {
// i1 is used to represent bool in C so is fairly well supported.
if (tagBits == 1)
return 1;
// Otherwise, round the physical size in bytes up to the next power of two.
// Round the physical size in bytes up to the next power of two.
unsigned tagBytes = (tagBits + 7U)/8U;
if (!llvm::isPowerOf2_32(tagBytes))
tagBytes = llvm::NextPowerOf2(tagBytes);
Expand Down Expand Up @@ -2221,15 +2218,9 @@ namespace {
// If any tag bits are present, they must match.
llvm::Value *tagResult = nullptr;
if (tagBits) {
if (ExtraTagBitCount == 1) {
if (extraTag == 1)
tagResult = tagBits;
else
tagResult = IGF.Builder.CreateNot(tagBits);
} else {
tagResult = IGF.Builder.CreateICmpEQ(tagBits,
llvm::ConstantInt::get(IGF.IGM.getLLVMContext(), extraTag));
}
tagResult = IGF.Builder.CreateICmpEQ(
tagBits,
llvm::ConstantInt::get(IGF.IGM.getLLVMContext(), extraTag));
}

if (tagResult && payloadResult)
Expand Down Expand Up @@ -2311,7 +2302,9 @@ namespace {
oneDest = llvm::BasicBlock::Create(C);
tagBitBlocks.push_back(oneDest);
}
IGF.Builder.CreateCondBr(tagBits, oneDest, zeroDest);
auto isOne = IGF.Builder.CreateICmpEQ(
tagBits, llvm::ConstantInt::get(tagBits->getType(), 1));
IGF.Builder.CreateCondBr(isOne, oneDest, zeroDest);
} else {
auto swi = SwitchBuilder::create(IGF, tagBits,
SwitchDefaultDest(unreachableBB, IsUnreachable),
Expand Down Expand Up @@ -2587,14 +2580,9 @@ namespace {
// If we have extra tag bits, they will be zero if we contain a payload.
if (ExtraTagBitCount > 0) {
assert(extraBits);
llvm::Value *isNonzero;
if (ExtraTagBitCount == 1) {
isNonzero = extraBits;
} else {
llvm::Value *zero = llvm::ConstantInt::get(extraBits->getType(), 0);
isNonzero = IGF.Builder.CreateICmp(llvm::CmpInst::ICMP_NE,
extraBits, zero);
}
llvm::Value *zero = llvm::ConstantInt::get(extraBits->getType(), 0);
llvm::Value *isNonzero =
IGF.Builder.CreateICmp(llvm::CmpInst::ICMP_NE, extraBits, zero);

auto *zeroBB = llvm::BasicBlock::Create(IGF.IGM.getLLVMContext());
IGF.Builder.CreateCondBr(isNonzero, nonzeroBB, zeroBB);
Expand Down
4 changes: 2 additions & 2 deletions test/IRGen/alignment.sil
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Expand Up @@ -57,10 +57,10 @@ entry:
store %w to %d : $*NoPayload

// CHECK: load i32{{.*}}, align 16
// CHECK: load i1{{.*}}, align 4
// CHECK: load i8{{.*}}, align 4
%v = load %e : $*SinglePayload
// CHECK: store i32{{.*}}, align 16
// CHECK: store i1{{.*}}, align 4
// CHECK: store i8{{.*}}, align 4
store %v to %e : $*SinglePayload

// CHECK: load i32{{.*}}, align 16
Expand Down
8 changes: 3 additions & 5 deletions test/IRGen/bitcast.sil
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Expand Up @@ -40,11 +40,9 @@ entry(%c : $C):

// CHECK-x86_64-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { i64, i8 } @bitcast_trivial_optional(i64 %0, i8 %1) {{.*}} {
// CHECK-x86_64-NEXT: entry:
// CHECK-x86_64-NEXT: %2 = trunc i8 %1 to i1
// CHECK-x86_64-NEXT: %3 = zext i1 %2 to i8
// CHECK-x86_64-NEXT: %4 = insertvalue { i64, i8 } undef, i64 %0, 0
// CHECK-x86_64-NEXT: %5 = insertvalue { i64, i8 } %4, i8 %3, 1
// CHECK-x86_64-NEXT: ret { i64, i8 } %5
// CHECK-x86_64-NEXT: %2 = insertvalue { i64, i8 } undef, i64 %0, 0
// CHECK-x86_64-NEXT: %3 = insertvalue { i64, i8 } %2, i8 %1, 1
// CHECK-x86_64-NEXT: ret { i64, i8 } %3

sil @bitcast_trivial_optional: $@convention(thin) (Optional<Int>) -> Optional<Int> {
entry(%c : $Optional<Int>):
Expand Down
39 changes: 20 additions & 19 deletions test/IRGen/enum.sil
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Expand Up @@ -470,10 +470,10 @@ enum SinglePayloadNoXI2 {
// CHECK-32: define{{( dllexport)?}}{{( protected)?}} swiftcc i1 @select_enum([[WORD:i32]] %0, i8 %1)
// CHECK-64: define{{( dllexport)?}}{{( protected)?}} swiftcc i1 @select_enum([[WORD:i64]] %0, i8 %1)
// CHECK: entry:
// CHECK: [[TAG:%.*]] = trunc i8 %1 to i1
// CHECK: [[PAYLOAD:%.*]] = icmp eq [[WORD]] %0, 1
// CHECK: [[MATCHES:%.*]] = and i1 [[TAG]], [[PAYLOAD]]
// CHECK: [[RES:%.*]] = select i1 [[MATCHES]], i1 false, i1 true
// CHECK: [[TAG:%.*]] = icmp eq i8 %1, 1
// CHECK: [[COMBINED:%.*]] = and i1 [[TAG]], [[PAYLOAD]]
// CHECK: [[RES:%.*]] = select i1 [[COMBINED]], i1 false, i1 true
// CHECK: ret i1 [[RES]]
// CHECK: }

Expand All @@ -490,7 +490,7 @@ bb0(%0 : $SinglePayloadNoXI2):
sil @single_payload_no_xi_switch : $@convention(thin) (SinglePayloadNoXI2) -> () {
// CHECK: entry:
entry(%u : $SinglePayloadNoXI2):
// CHECK: %2 = trunc i8
// CHECK: %2 = icmp eq i8 %1, 1
// CHECK: br i1 %2, label %[[TAGS:[0-9]+]], label %[[X_DEST:[0-9]+]]
// CHECK: [[TAGS]]:
// CHECK: switch [[WORD]] %0, label %[[DFLT:[0-9]+]] [
Expand Down Expand Up @@ -564,7 +564,7 @@ end:
sil @single_payload_no_xi_switch_arg : $@convention(thin) (SinglePayloadNoXI2) -> () {
// CHECK: entry:
entry(%u : $SinglePayloadNoXI2):
// CHECK: %2 = trunc i8
// CHECK: %2 = icmp eq i8 %1, 1
// CHECK: br i1 %2, label %[[TAGS:[0-9]+]], label %[[X_PREDEST:[0-9]+]]
// CHECK: [[TAGS]]:
// CHECK: switch [[WORD]] %0, label %[[DFLT:[0-9]+]] [
Expand Down Expand Up @@ -633,7 +633,7 @@ entry(%0 : $Builtin.Word):
// CHECK: entry:
// CHECK: store [[WORD]] %0, ptr %1
// CHECK: [[T0:%.*]] = getelementptr inbounds %T4enum18SinglePayloadNoXI2O, ptr %1, i32 0, i32 1
// CHECK: store i1 false, ptr [[T0]]
// CHECK: store i8 0, ptr [[T0]]
// CHECK: ret void
// CHECK: }
sil @single_payload_no_xi_inject_x_indirect : $(Builtin.Word, @inout SinglePayloadNoXI2) -> () {
Expand All @@ -659,7 +659,7 @@ entry:
// CHECK: entry:
// CHECK: store [[WORD]] 0, ptr %0
// CHECK: [[T0:%.*]] = getelementptr inbounds %T4enum18SinglePayloadNoXI2O, ptr %0, i32 0, i32 1
// CHECK: store i1 true, ptr [[T0]]
// CHECK: store i8 1, ptr [[T0]]
// CHECK: ret void
// CHECK: }
sil @single_payload_no_xi_inject_y_indirect : $(@inout SinglePayloadNoXI2) -> () {
Expand Down Expand Up @@ -1593,12 +1593,10 @@ enum MultiPayloadOneSpareBit {
// CHECK-64: define{{( dllexport)?}}{{( protected)?}} swiftcc void @multi_payload_one_spare_bit_switch(i64 %0, i8 %1) {{.*}} {
sil @multi_payload_one_spare_bit_switch : $(MultiPayloadOneSpareBit) -> () {
entry(%u : $MultiPayloadOneSpareBit):
// CHECK-64: [[NATIVECC_TRUNC:%.*]] = trunc i8 %1 to i1
// CHECK-64: [[SPARE_TAG_LSHR:%.*]] = lshr i64 %0, 63
// CHECK-64: [[SPARE_TAG_TRUNC:%.*]] = trunc i64 [[SPARE_TAG_LSHR]] to i8
// CHECK-64: [[SPARE_TAG:%.*]] = and i8 [[SPARE_TAG_TRUNC]], 1
// CHECK-64: [[EXTRA_TAG_ZEXT:%.*]] = zext i1 [[NATIVECC_TRUNC]] to i8
// CHECK-64: [[EXTRA_TAG:%.*]] = shl i8 [[EXTRA_TAG_ZEXT]], 1
// CHECK-64: [[EXTRA_TAG:%.*]] = shl i8 %1, 1
// CHECK-64: [[TAG:%.*]] = or i8 [[SPARE_TAG]], [[EXTRA_TAG]]
// CHECK-64: switch i8 [[TAG]], label %[[UNREACHABLE:[0-9]+]] [
// CHECK-64: i8 0, label %[[X_PREDEST:[0-9]+]]
Expand Down Expand Up @@ -1681,7 +1679,7 @@ sil @multi_payload_one_spare_bit_switch_indirect : $(@inout MultiPayloadOneSpare
entry(%u : $*MultiPayloadOneSpareBit):
// CHECK-64: [[PAYLOAD:%.*]] = load i64, ptr %0
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T4enum23MultiPayloadOneSpareBitO, ptr %0, i32 0, i32 1
// CHECK-64: [[TAG:%.*]] = load i1, ptr [[T0]]
// CHECK-64: [[TAG:%.*]] = load i8, ptr [[T0]]
// CHECK-64: switch i8 {{%.*}}
// CHECK-64: switch i64 [[PAYLOAD]]
// CHECK-64: {{[0-9]+}}:
Expand Down Expand Up @@ -1748,7 +1746,7 @@ entry(%0 : $Builtin.Int62):
// CHECK-64: [[PAYLOAD_MASKED:%.*]] = and i64 [[PAYLOAD]], 9223372036854775807
// CHECK-64: store i64 [[PAYLOAD_MASKED]], ptr %1
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T4enum23MultiPayloadOneSpareBitO, ptr %1, i32 0, i32 1
// CHECK-64: store i1 false, ptr [[T0]]
// CHECK-64: store i8 0, ptr [[T0]]
// CHECK-64: ret void
// CHECK-64: }
sil @multi_payload_one_spare_bit_inject_x_indirect : $(Builtin.Int62, @inout MultiPayloadOneSpareBit) -> () {
Expand Down Expand Up @@ -1788,7 +1786,7 @@ entry(%0 : $Builtin.Int63):
// CHECK-64: [[PAYLOAD_TAGGED:%.*]] = or i64 [[PAYLOAD_MASKED]], -9223372036854775808
// CHECK-64: store i64 [[PAYLOAD_TAGGED]], ptr %1
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T4enum23MultiPayloadOneSpareBitO, ptr %1, i32 0, i32 1
// CHECK-64: store i1 false, ptr [[T0]]
// CHECK-64: store i8 0, ptr [[T0]]
// CHECK-64: ret void
// CHECK-64: }

Expand Down Expand Up @@ -1831,7 +1829,7 @@ entry:
// -- 0x8000_0000_0000_0000
// CHECK-64: store i64 -9223372036854775808, ptr %0
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T4enum23MultiPayloadOneSpareBitO, ptr %0, i32 0, i32 1
// CHECK-64: store i1 true, ptr [[T0]]
// CHECK-64: store i8 1, ptr [[T0]]
// CHECK-64: ret void
// CHECK-64: }
sil @multi_payload_one_spare_bit_inject_a_indirect : $(@inout MultiPayloadOneSpareBit) -> () {
Expand Down Expand Up @@ -2227,8 +2225,9 @@ enum MultiPayloadNested {
// CHECK: %3 = getelementptr
// CHECK: %4 = load i8, ptr %3
// CHECK: %5 = lshr i8 %4, 7
// CHECK: %6 = trunc i8 %5 to i1
// CHECK: br i1 %6
// CHECK: %6 = and i8 %5, 1
// CHECK: %7 = icmp ne i8 %6, 1
// CHECK: br i1 %7
sil @multi_payload_nested_switch : $(@in MultiPayloadNested) -> () {
entry(%c : $*MultiPayloadNested):
switch_enum_addr %c : $*MultiPayloadNested, case #MultiPayloadNested.A!enumelt: a_dest, case #MultiPayloadNested.B!enumelt: b_dest
Expand Down Expand Up @@ -2259,8 +2258,10 @@ enum MultiPayloadNestedSpareBits {
// CHECK-64: entry:
// CHECK-64: %1 = load [[WORD]], ptr %0
// CHECK-64: %2 = lshr [[WORD]] %1, 61
// CHECK-64: %3 = trunc [[WORD]] %2 to i1
// CHECK-64: br i1 %3
// CHECK-64: %3 = trunc [[WORD]] %2 to i8
// CHECK-64: %4 = and i8 %3, 1
// CHECK-64: %5 = icmp ne i8 %4, 1
// CHECK-64: br i1 %5
sil @multi_payload_nested_spare_bits_switch : $(@in MultiPayloadNestedSpareBits) -> () {
entry(%c : $*MultiPayloadNestedSpareBits):
switch_enum_addr %c : $*MultiPayloadNestedSpareBits, case #MultiPayloadNestedSpareBits.A!enumelt: a_dest, case #MultiPayloadNestedSpareBits.B!enumelt: b_dest
Expand Down Expand Up @@ -2459,7 +2460,7 @@ entry(%x : $Int32):
// CHECK-64: [[INT_ZEXT:%.*]] = zext i32 %0 to i64
// CHECK-64: [[INT_SHL:%.*]] = shl i64 [[INT_ZEXT]], 32
%d = enum $Optional<(Optional<()>, Int32)>, #Optional.some!enumelt, %c : $(Optional<()>, Int32)
// CHECK-64: [[BIT:%.*]] = trunc i64 [[INT_SHL]] to i1
// CHECK-64: [[BIT:%.*]] = trunc i64 [[INT_SHL]] to i8
// CHECK-64: [[INT_SHR:%.*]] = lshr i64 [[INT_SHL]], 32
// CHECK-64: [[INT:%.*]] = trunc i64 [[INT_SHR]] to i32
%e = unchecked_enum_data %d : $Optional<(Optional<()>, Int32)>, #Optional.some!enumelt
Expand Down
6 changes: 3 additions & 3 deletions test/IRGen/enum_copy_init_with_take_memcpy.swift
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Expand Up @@ -30,9 +30,9 @@ struct HasAnEnum {
// CHECK: define {{.*}} swiftcc range(i64 -1, 5) i64 @"$s31enum_copy_init_with_take_memcpy9HasAnEnumV9readValueSiyF"(ptr {{.*}} %0)
// CHECK: [[T0:%.*]] = getelementptr inbounds i8, ptr %0, i64 160
// CHECK: [[T1:%.*]] = load i8, ptr [[T0]]
// CHECK: [[T2:%.*]] = icmp eq i8 [[T1]], 2
// CHECK: br i1 [[T2]], label
// CHECK: [[R:%.*]] = phi i64 [ -1, {{.*}} ], [ 4, {{.*}} ]
// CHECK: [[T2:%.*]] = and i8 [[T1]], -3
// CHECK: [[T3:%.*]] = icmp eq i8 [[T2]], 0
// CHECK: [[R:%.*]] = select i1 [[T3]], i64 -1, i64 4
// CHECK: ret i64 [[R]]

}
8 changes: 4 additions & 4 deletions test/IRGen/enum_dynamic_multi_payload.sil
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Expand Up @@ -40,21 +40,21 @@ entry(%e : $Either<(), ()>):
fix_lifetime %e : $Either<(), ()>

// CHECK-NEXT: alloca
// CHECK-NEXT: trunc i8 {{.*}} to i1
// CHECK-NEXT: llvm.lifetime.start
%s = alloc_stack $Either<(), ()>

%l = enum $Either<(), ()>, #Either.Left!enumelt, undef : $()
// CHECK-NEXT: store i1 false
// CHECK-NEXT: store i8 0
store %l to %s : $*Either<(), ()>
%r = enum $Either<(), ()>, #Either.Right!enumelt, undef : $()
// CHECK-NEXT: store i1 true
// CHECK-NEXT: store i8 1
// CHECK-NEXT: [[COND:%.*]] = icmp ne i8 {{%.*}}, 1
store %r to %s : $*Either<(), ()>

%a = unchecked_enum_data %l : $Either<(), ()>, #Either.Left!enumelt
%b = unchecked_enum_data %r : $Either<(), ()>, #Either.Right!enumelt

// CHECK-NEXT: br i1 {{%.*}}, label %[[RIGHT_PRE:[0-9]+]], label %[[LEFT_PRE:[0-9]+]]
// CHECK-NEXT: br i1 [[COND]], label %[[LEFT_PRE:[0-9]+]], label %[[RIGHT_PRE:[0-9]+]]
// CHECK: [[LEFT_PRE]]:
// CHECK: br label [[LEFT:%[0-9]+]]
// CHECK: [[RIGHT_PRE]]:
Expand Down
35 changes: 18 additions & 17 deletions test/IRGen/enum_future.sil
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Expand Up @@ -474,8 +474,8 @@ enum SinglePayloadNoXI2 {
// CHECK-32: define{{( dllexport)?}}{{( protected)?}} swiftcc i1 @select_enum([[WORD:i32]] %0, i8 %1)
// CHECK-64: define{{( dllexport)?}}{{( protected)?}} swiftcc i1 @select_enum([[WORD:i64]] %0, i8 %1)
// CHECK: entry:
// CHECK: [[TAG:%.*]] = trunc i8 %1 to i1
// CHECK: [[PAYLOAD:%.*]] = icmp eq [[WORD]] %0, 1
// CHECK: [[TAG:%.*]] = icmp eq i8 %1, 1
// CHECK: [[MATCHES:%.*]] = and i1 [[TAG]], [[PAYLOAD]]
// CHECK: [[RES:%.*]] = select i1 [[MATCHES]], i1 false, i1 true
// CHECK: ret i1 [[RES]]
Expand All @@ -494,7 +494,7 @@ bb0(%0 : $SinglePayloadNoXI2):
sil @single_payload_no_xi_switch : $@convention(thin) (SinglePayloadNoXI2) -> () {
// CHECK: entry:
entry(%u : $SinglePayloadNoXI2):
// CHECK: %2 = trunc i8
// CHECK: %2 = icmp eq i8 %1, 1
// CHECK: br i1 %2, label %[[TAGS:[0-9]+]], label %[[X_DEST:[0-9]+]]
// CHECK: [[TAGS]]:
// CHECK: switch [[WORD]] %0, label %[[DFLT:[0-9]+]] [
Expand Down Expand Up @@ -568,7 +568,7 @@ end:
sil @single_payload_no_xi_switch_arg : $@convention(thin) (SinglePayloadNoXI2) -> () {
// CHECK: entry:
entry(%u : $SinglePayloadNoXI2):
// CHECK: %2 = trunc i8
// CHECK: %2 = icmp eq i8 %1, 1
// CHECK: br i1 %2, label %[[TAGS:[0-9]+]], label %[[X_PREDEST:[0-9]+]]
// CHECK: [[TAGS]]:
// CHECK: switch [[WORD]] %0, label %[[DFLT:[0-9]+]] [
Expand Down Expand Up @@ -637,7 +637,7 @@ entry(%0 : $Builtin.Word):
// CHECK: entry:
// CHECK: store [[WORD]] %0, ptr %1
// CHECK: [[T0:%.*]] = getelementptr inbounds %T11enum_future18SinglePayloadNoXI2O, ptr %1, i32 0, i32 1
// CHECK: store i1 false, ptr [[T0]]
// CHECK: store i8 0, ptr [[T0]]
// CHECK: ret void
// CHECK: }
sil @single_payload_no_xi_inject_x_indirect : $(Builtin.Word, @inout SinglePayloadNoXI2) -> () {
Expand All @@ -663,7 +663,7 @@ entry:
// CHECK: entry:
// CHECK: store [[WORD]] 0, ptr %0
// CHECK: [[T0:%.*]] = getelementptr inbounds %T11enum_future18SinglePayloadNoXI2O, ptr %0, i32 0, i32 1
// CHECK: store i1 true, ptr [[T0]]
// CHECK: store i8 1, ptr [[T0]]
// CHECK: ret void
// CHECK: }
sil @single_payload_no_xi_inject_y_indirect : $(@inout SinglePayloadNoXI2) -> () {
Expand Down Expand Up @@ -1597,12 +1597,10 @@ enum MultiPayloadOneSpareBit {
// CHECK-64: define{{( dllexport)?}}{{( protected)?}} swiftcc void @multi_payload_one_spare_bit_switch(i64 %0, i8 %1) {{.*}} {
sil @multi_payload_one_spare_bit_switch : $(MultiPayloadOneSpareBit) -> () {
entry(%u : $MultiPayloadOneSpareBit):
// CHECK-64: [[NATIVECC_TRUNC:%.*]] = trunc i8 %1 to i1
// CHECK-64: [[SPARE_TAG_LSHR:%.*]] = lshr i64 %0, 63
// CHECK-64: [[SPARE_TAG_TRUNC:%.*]] = trunc i64 [[SPARE_TAG_LSHR]] to i8
// CHECK-64: [[SPARE_TAG:%.*]] = and i8 [[SPARE_TAG_TRUNC]], 1
// CHECK-64: [[EXTRA_TAG_ZEXT:%.*]] = zext i1 [[NATIVECC_TRUNC]] to i8
// CHECK-64: [[EXTRA_TAG:%.*]] = shl i8 [[EXTRA_TAG_ZEXT]], 1
// CHECK-64: [[EXTRA_TAG:%.*]] = shl i8 %1, 1
// CHECK-64: [[TAG:%.*]] = or i8 [[SPARE_TAG]], [[EXTRA_TAG]]
// CHECK-64: switch i8 [[TAG]], label %[[UNREACHABLE:[0-9]+]] [
// CHECK-64: i8 0, label %[[X_PREDEST:[0-9]+]]
Expand Down Expand Up @@ -1685,7 +1683,7 @@ sil @multi_payload_one_spare_bit_switch_indirect : $(@inout MultiPayloadOneSpare
entry(%u : $*MultiPayloadOneSpareBit):
// CHECK-64: [[PAYLOAD:%.*]] = load i64, ptr %0
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T11enum_future23MultiPayloadOneSpareBitO, ptr %0, i32 0, i32 1
// CHECK-64: [[TAG:%.*]] = load i1, ptr [[T0]]
// CHECK-64: [[TAG:%.*]] = load i8, ptr [[T0]]
// CHECK-64: switch i8 {{%.*}}
// CHECK-64: switch i64 [[PAYLOAD]]
// CHECK-64: {{[0-9]+}}:
Expand Down Expand Up @@ -1752,7 +1750,7 @@ entry(%0 : $Builtin.Int62):
// CHECK-64: [[PAYLOAD_MASKED:%.*]] = and i64 [[PAYLOAD]], 9223372036854775807
// CHECK-64: store i64 [[PAYLOAD_MASKED]], ptr %1
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T11enum_future23MultiPayloadOneSpareBitO, ptr %1, i32 0, i32 1
// CHECK-64: store i1 false, ptr [[T0]]
// CHECK-64: store i8 0, ptr [[T0]]
// CHECK-64: ret void
// CHECK-64: }
sil @multi_payload_one_spare_bit_inject_x_indirect : $(Builtin.Int62, @inout MultiPayloadOneSpareBit) -> () {
Expand Down Expand Up @@ -1792,7 +1790,7 @@ entry(%0 : $Builtin.Int63):
// CHECK-64: [[PAYLOAD_TAGGED:%.*]] = or i64 [[PAYLOAD_MASKED]], -9223372036854775808
// CHECK-64: store i64 [[PAYLOAD_TAGGED]], ptr %1
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T11enum_future23MultiPayloadOneSpareBitO, ptr %1, i32 0, i32 1
// CHECK-64: store i1 false, ptr [[T0]]
// CHECK-64: store i8 0, ptr [[T0]]
// CHECK-64: ret void
// CHECK-64: }

Expand Down Expand Up @@ -1835,7 +1833,7 @@ entry:
// -- 0x8000_0000_0000_0000
// CHECK-64: store i64 -9223372036854775808, ptr %0
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T11enum_future23MultiPayloadOneSpareBitO, ptr %0, i32 0, i32 1
// CHECK-64: store i1 true, ptr [[T0]]
// CHECK-64: store i8 1, ptr [[T0]]
// CHECK-64: ret void
// CHECK-64: }
sil @multi_payload_one_spare_bit_inject_a_indirect : $(@inout MultiPayloadOneSpareBit) -> () {
Expand Down Expand Up @@ -2231,8 +2229,9 @@ enum MultiPayloadNested {
// CHECK: %3 = getelementptr
// CHECK: %4 = load i8, ptr %3
// CHECK: %5 = lshr i8 %4, 7
// CHECK: %6 = trunc i8 %5 to i1
// CHECK: br i1 %6
// CHECK: %6 = and i8 %5, 1
// CHECK: %7 = icmp ne i8 %6, 1
// CHECK: br i1 %7
sil @multi_payload_nested_switch : $(@in MultiPayloadNested) -> () {
entry(%c : $*MultiPayloadNested):
switch_enum_addr %c : $*MultiPayloadNested, case #MultiPayloadNested.A!enumelt: a_dest, case #MultiPayloadNested.B!enumelt: b_dest
Expand Down Expand Up @@ -2263,8 +2262,10 @@ enum MultiPayloadNestedSpareBits {
// CHECK-64: entry:
// CHECK-64: %1 = load [[WORD]], ptr %0
// CHECK-64: %2 = lshr [[WORD]] %1, 61
// CHECK-64: %3 = trunc [[WORD]] %2 to i1
// CHECK-64: br i1 %3
// CHECK-64: %3 = trunc [[WORD]] %2 to i8
// CHECK-64: %4 = and i8 %3, 1
// CHECK-64: %5 = icmp ne i8 %4, 1
// CHECK-64: br i1 %5
sil @multi_payload_nested_spare_bits_switch : $(@in MultiPayloadNestedSpareBits) -> () {
entry(%c : $*MultiPayloadNestedSpareBits):
switch_enum_addr %c : $*MultiPayloadNestedSpareBits, case #MultiPayloadNestedSpareBits.A!enumelt: a_dest, case #MultiPayloadNestedSpareBits.B!enumelt: b_dest
Expand Down Expand Up @@ -2463,7 +2464,7 @@ entry(%x : $Int32):
// CHECK-64: [[INT_ZEXT:%.*]] = zext i32 %0 to i64
// CHECK-64: [[INT_SHL:%.*]] = shl i64 [[INT_ZEXT]], 32
%d = enum $Optional<(Optional<()>, Int32)>, #Optional.some!enumelt, %c : $(Optional<()>, Int32)
// CHECK-64: [[BIT:%.*]] = trunc i64 [[INT_SHL]] to i1
// CHECK-64: [[BIT:%.*]] = trunc i64 [[INT_SHL]] to i8
// CHECK-64: [[INT_SHR:%.*]] = lshr i64 [[INT_SHL]], 32
// CHECK-64: [[INT:%.*]] = trunc i64 [[INT_SHR]] to i32
%e = unchecked_enum_data %d : $Optional<(Optional<()>, Int32)>, #Optional.some!enumelt
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