Add CORDIC accelerator (RoCC + MMIO configs, test programs)

build.sbt

@@ -149,7 +149,7 @@ lazy val chipyard = (project in file("generators/chipyard"))
   .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
     sha3, // On separate line to allow for cleaner tutorial-setup patches
     dsptools, rocket_dsp_utils,
-    gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
+    gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,cordic,
     constellation, mempress, barf, shuttle, caliptra_aes)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(
@@ -311,3 +311,8 @@ lazy val fpga_shells = (project in file("./fpga/fpga-shells"))
 lazy val fpga_platforms = (project in file("./fpga"))
   .dependsOn(chipyard, fpga_shells)
   .settings(commonSettings)
+
+lazy val cordic = (project in file("generators/cordic"))
+  .dependsOn(rocketchip, rocket_dsp_utils)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(commonSettings)

fpga/src/main/scala/nexysvideo/Configs.scala

@@ -5,7 +5,7 @@ import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.lazymodule._
 import freechips.rocketchip.system._
 import freechips.rocketchip.tile._
 
@@ -22,18 +22,23 @@ class WithNoDesignKey extends Config((site, here, up) => {
 })
 
 // DOC include start: WithNexysVideoTweaks and Rocket
+
 class WithNexysVideoTweaks extends Config(
+ new freechips.rocketchip.subsystem.WithRoccExample ++
+  new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
+  new cordic.WithCORDIC(useAXI4=false, useBlackBox=true) ++         
   new WithNexysVideoUARTTSI ++
   new WithNexysVideoDDRTL ++
   new WithNoDesignKey ++
   new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
-  new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
-  new chipyard.config.WithMemoryBusFrequency(50.0) ++
-  new chipyard.config.WithFrontBusFrequency(50.0) ++
-  new chipyard.config.WithSystemBusFrequency(50.0) ++
-  new chipyard.config.WithPeripheryBusFrequency(50.0) ++
-  new chipyard.config.WithControlBusFrequency(50.0) ++
+
+  new chipyard.harness.WithHarnessBinderClockFreqMHz(10) ++
+  new chipyard.config.WithMemoryBusFrequency(10.0) ++
+  new chipyard.config.WithFrontBusFrequency(10.0) ++
+  new chipyard.config.WithSystemBusFrequency(10.0) ++
+  new chipyard.config.WithPeripheryBusFrequency(10.0) ++
+  new chipyard.config.WithControlBusFrequency(10.0) ++
   new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
   new chipyard.config.WithNoDebug ++ // no jtag
@@ -72,3 +77,9 @@ class TinyRocketNexysVideoConfig extends Config(
   new chipyard.config.WithBroadcastManager ++ // no l2
   new chipyard.TinyRocketConfig)
   // DOC include end: WithTinyNexysVideoTweaks and Rocket
+
+class BringupNexysVideoConfig extends Config(
+  new WithNexysVideoSerialTLToGPIO ++
+  new WithNexysVideoTweaks(freqMHz = 75) ++
+  new chipyard.ChipBringupHostConfig)
+

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -7,6 +7,8 @@ import freechips.rocketchip.system._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.devices.tilelink._
 
+import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
+import cordic.WithCORDIC
 // ------------------------------------
 // BOOM and/or Rocket Top Level Systems
 // ------------------------------------
@@ -37,6 +39,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port
   with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block
   with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect
+  with cordic.CanHavePeripheryCORDIC // Enables optionally having an MMIO-based CORDIC block
 {
   override lazy val module = new DigitalTopModule(this)
 }

generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala

@@ -58,10 +58,17 @@ class LargeNVDLARocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
+
 class ManyMMIOAcceleratorRocketConfig extends Config(
+
+  new freechips.rocketchip.subsystem.WithRoccExample ++
   new chipyard.harness.WithDontTouchChipTopPorts(false) ++   // TODO: hack around dontTouch not working in SFC
+
   new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
+  new cordic.WithCORDIC(useAXI4=false, useBlackBox=true) ++         
   new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
   new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR
+
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.AbstractConfig)
+  new chipyard.config.AbstractConfig
+  )