[Bugfix] Route DSv4 sparse-indexer prefill top-k around NaN-broken kernel path on SM12x

[linjiapro]

FIX #49896 (the crash layer; the NaN-logits layer of that issue remains open).

Purpose

DeepSeek-V4-Flash on SM12x (enabled by #43477) crashes with a CUDA illegal memory access on the first prefill longer than ~2048 tokens. Root cause chain (full tensor-level evidence in #49896):

1. fp8_fp4_mqa_logits emits NaN-dominated logits on SM12x (83→100% NaN cascade).
2. top_k_per_row_prefill's histogram path (rows with more candidates than top_k) mishandles NaN input: it writes NaN bit patterns (0x7FC00000 = 2143289344) as candidate indices and leaves part of its dynamic-smem output unwritten, copying uninitialized memory out as indices. Reproducible in a 25-line standalone script (see the issue); with clean input the kernel is correct on SM120 (upstream unit test passes 12/12 here).
3. compute_global_topk_indices_and_lens trusts local_idx >= 0 and gathers block_table[req, INT32_MAX // block_size] → IMA on all TP ranks.

This PR routes SM12x prefill top-k through a torch.topk implementation of the kernel's documented contract: top-k of logits[i, ks_i:ke_i) relative to ks_i, ascending position order, -1 padding for short rows, NaN never selected. It mirrors the decode path, which already excludes SM12x from cooperative_topk.

Deliberately narrow:

• Not a csrc change: the kernel's NaN mishandling is data-driven and deserves hardening for every arch (never emit unwritten smem; exclude NaN), but we cannot build/test csrc on the affected hardware — left to the issue.
• Not a fix for the NaN logits themselves (the primary SM12x defect; cf. the e8m0→fp32 upcast and SM120 DeepGEMM fallbacks in [New Model][Nvidia] Add SM12x support for DeepSeek V4 Flash with essential fixes #41834). With NaN scores, any correct top-k selects an arbitrary candidate set, so SM12x DSv4 output quality for long prompts remains degraded until that lands. This PR converts a hard engine crash into defined, contract-correct behavior and is a prerequisite for any further SM12x DSv4 work.

Test Plan

• New contract test test_top_k_per_row_prefill_torch_fallback (runs on any CUDA device): set-equality with the torch.topk reference per row, ascending order, in-range, -1 padding, NaN exclusion.
• Real-workload validation on 4× RTX PRO 6000 Blackwell Workstation (SM120, TP=4), vLLM 0.26.0 + flashinfer 0.6.14, DeepSeek-V4-Flash: the previously 9×-reproducible crash (16 concurrent structured-output requests, mixed 0.5–8K-token prefill) is eliminated — zero illegal memory accesses, zero garbage indices in the consumer across repeated full fan-outs; engine survives and serves.

Test Result

• test_top_k_per_row_prefill_torch_fallback: 6/6 pass on SM120.
• Existing test_top_k_per_row (CUDA kernel, clean inputs): 12/12 pass on SM120, unaffected by this change.

[claude]

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