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Introduce CY8CPROTO_041TP EVK
Add support for Infineon CAT2 HAL

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split into proper commits e.g. for adding soc, for adding board, look at https://docs.zephyrproject.org/latest/contribute/style/kconfig.html and read and apply rules before re-requesting review

@manoj-aerlync manoj-aerlync force-pushed the cy8cproto_041tp_introduction branch 4 times, most recently from 929d3b7 to 2ce5f0a Compare October 30, 2025 12:15
@zephyrbot zephyrbot requested a review from nordic-krch October 30, 2025 12:35
@manoj-aerlync manoj-aerlync force-pushed the cy8cproto_041tp_introduction branch from dfcbfbf to c8effe6 Compare October 30, 2025 12:51
@manoj-aerlync manoj-aerlync marked this pull request as draft October 30, 2025 13:13
@dharunkrithikk dharunkrithikk force-pushed the cy8cproto_041tp_introduction branch from 5bf7770 to 8d4df53 Compare October 30, 2025 13:35
@Deepika-aerlync Deepika-aerlync force-pushed the cy8cproto_041tp_introduction branch from 8d4df53 to b42f3ce Compare October 30, 2025 14:41
@dharunkrithikk dharunkrithikk force-pushed the cy8cproto_041tp_introduction branch 4 times, most recently from 56cd6da to 0de383f Compare November 4, 2025 04:55
@manoj-aerlync manoj-aerlync marked this pull request as ready for review November 4, 2025 04:57
@zephyrbot zephyrbot added area: Pinctrl area: UART Universal Asynchronous Receiver-Transmitter area: I2C area: SPI SPI bus area: Counter labels Nov 4, 2025
@zephyrbot zephyrbot requested a review from dcpleung November 4, 2025 04:59
# SPDX-License-Identifier: Apache-2.0

add_subdirectory(${SOC_SERIES})
zephyr_compile_definitions($<UPPER_CASE:${CONFIG_SOC}>_${CONFIG_SOC_PART_NUMBER})
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Is this required? is it not taken care by the infineon_kconfig.h?

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This line is removed from the CMakeLists.txt.

# Copyright (c) 2025 Infineon Technologies AG,
# or an affiliate of Infineon Technologies AG.
#
# SPDX-License-Identifier: Apache-2.0
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Please use psoc4 instead of cat2 for folder names as well as other places (like variable names)

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Replaced cat2 with psoc4 as suggested in all places.

- hal
- name: hal_infineon
revision: f3c571f772209b5970bdd1806da641244b5c4c38
revision: 2d37de92236ea62b80562e7381ff43d9522dbbad
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please use pull/34 till its merged into hal_infineon

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got merged so no changes done

OR CONFIG_SOC_FAMILY_INFINEON_CAT1
OR CONFIG_SOC_FAMILY_INFINEON_EDGE)
OR CONFIG_SOC_FAMILY_INFINEON_EDGE
OR CONFIG_SOC_FAMILY_INFINEON_CAT2)
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Suggested change
OR CONFIG_SOC_FAMILY_INFINEON_CAT2)
OR CONFIG_SOC_FAMILY_INFINEON_PSOC4)

Please make this change throughout the PR

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Changed CAT2 to PSCO4 throughout the PR.

Comment on lines 118 to 137
config USE_INFINEON_LP_COMP
bool
help
Enable LP-Comp (Low-Power Comparator) HAL module driver for Infineon devices

config USE_INFINEON_MSCLP
bool
help
Enable MSCLP (Multi-Speed Clock Low-Power) HAL module driver for Infineon devices

config USE_INFINEON_TCPWM_QUADDEC
bool
help
Enable Timer (Timer/Counter/PWM Quadrature Decoder) HAL module driver for
Infineon devices

config USE_INFINEON_SMARTIO
bool
help
Enable Smart-IO module driver for Infineon devices
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I would recommend dropping these since these peripherals are not yet supported

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Dropped above mentioned peripherals.

Comment on lines 14 to 18
zephyr_library_compile_definitions(CONFIG_SOC_PART_NUMBER)
zephyr_library_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT2 $<UPPER_CASE:${CONFIG_SOC}>)

# Generate PDL specific define (w. *_device) for SOC module
zephyr_library_compile_definitions_ifdef(CONFIG_SOC_PART_NUMBER ${CONFIG_SOC_PART_NUMBER}_device)
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Suggested change
zephyr_library_compile_definitions(CONFIG_SOC_PART_NUMBER)
zephyr_library_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT2 $<UPPER_CASE:${CONFIG_SOC}>)
# Generate PDL specific define (w. *_device) for SOC module
zephyr_library_compile_definitions_ifdef(CONFIG_SOC_PART_NUMBER ${CONFIG_SOC_PART_NUMBER}_device)
zephyr_library_compile_definitions(CONFIG_SOC_PART_NUMBER)
zephyr_library_compile_definitions($<UPPER_CASE:${CONFIG_SOC}>)
zephyr_library_compile_definitions(${CONFIG_SOC_PART_NUMBER}_device)

Remove redundant checks

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changed


# Include directories
zephyr_include_directories(${pdl_drv_dir}/include)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT2 ${pdl_dev_dir}/include)
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Checking for CONFIG_SOC_FAMILY_INFINEON_CAT2 is redundant since this file is included only if its CONFIG_SOC_FAMILY_INFINEON_CAT2. Please update throughout the file

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updated

#
# SPDX-License-Identifier: Apache-2.0

description: Infineon Serial Communication Blocks (SCB) node
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Why do we need a separate binding file for UART?

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changed using existing one

.. target-notes::

.. _cy8cproto_041tp Board Website:
https://www.infineon.com/assets/row/public/documents/30/57/infineon-psoc-4100t-plus-architecture-trm-additionaltechnicalinformation-en.pdf
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This link points to the TRM for the PSOC 4100T Plus MCU, not the board website.

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Placed the link for cy8cproto_041tp Board Website

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This file looks like a duplicate of options defined in Kconfig.ifx_cat1, so I don't think this file is necessary.

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Removed the Kconfig.ifx_cat2 file.

Comment on lines 89 to 97
#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT2)
Cy_SysClk_ImoEnable();
int err = Cy_SysClk_ImoSetFrequency(config->rate);

if (err != CY_SYSCLK_SUCCESS) {
printk("Failed to set IMO frequency with (error: %d)\n", err);
return -EIO;
}
#endif
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Can these use device tree (as done for clk_pilo) instead of soc family for better portability between devices?

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Cy_SysClk_ImoSetFrequency is not there in cat1 so checked with dts above this case, as well as used psoc4 for checking imo set freq alone.

Comment on lines 103 to 107
#if !defined(CONFIG_SOC_FAMILY_INFINEON_CAT2)
case IFX_IHO:
Cy_SysClk_IhoEnable();
break;
#endif
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Can these use device tree (as done for clk_pilo) instead of soc family for better portability between devices?

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used dts to check, changed

Comment on lines 36 to 40
#define CONVERT_UART_STOP_BITS_Z_TO_CY(sb) \
(((sb) <= UART_CFG_STOP_BITS_2) ? stop_bits_lut[(sb)] : CY_SCB_UART_STOP_BITS_1)

#define CONVERT_UART_DATA_BITS_Z_TO_CY(db) \
(((db) <= UART_CFG_DATA_BITS_9) ? data_bits_lut[(db)] : 1U)
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Rather than fail silently in the case of misconfiguration, it'd be better to log a warning or provide some other feedback.

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Updated the code to use LOG_WRN

.. _cy8cproto_041tp Board Website:
https://www.infineon.com/assets/row/public/documents/30/57/infineon-psoc-4100t-plus-architecture-trm-additionaltechnicalinformation-en.pdf

.. _ModusToolbox:
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Placed given link for ModusToolbox

https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox

.. _ModusToolbox Programming Tools:
https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxprogtools
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Placed above given link for ModusToolbox Programming Tool

Comment on lines 584 to 601
#if !defined(CONFIG_SOC_SERIES_PSOC4100TP)
.rxFifoTriggerLevel = 63UL,
#else
.rxFifoTriggerLevel = 7,
#endif
.rxFifoIntEnableMask = 0UL,
#if !defined(CONFIG_SOC_SERIES_PSOC4100TP)
.txFifoTriggerLevel = 63UL,
#else
.txFifoTriggerLevel = 0,
#endif
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Rather than use hardcoded magic numbers here that differ between parts, I'd rather see #define values. I think it makes the structure definition more readable.

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Replaced the hard-coded values with macros.

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Pinmux definitions are missing for 44-pin and 48-pin parts.

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Included pinmux definitions for 44-pin variant.

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Pinmux definitions are missing for 44-pin and 48-pin parts.

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Included pinmux definitions for 48-pin variant.

Comment on lines 34 to 51
#define CONVERT_UART_PARITY_Z_TO_CY(parity) (parity_lut[(parity)])

#define CONVERT_UART_STOP_BITS_Z_TO_CY(sb) \
(((sb) <= UART_CFG_STOP_BITS_2) ? stop_bits_lut[(sb)] : CY_SCB_UART_STOP_BITS_1)

#define CONVERT_UART_DATA_BITS_Z_TO_CY(db) \
(((db) <= UART_CFG_DATA_BITS_9) ? data_bits_lut[(db)] : 1U)

#define IFX_UART_BAUD_DIFF(actual, baud) \
(((actual) > (baud)) ? (((actual) * 100U - (baud) * 100U) / (baud)) \
: (((baud) * 100U - (actual) * 100U) / (baud)))

#define IFX_UART_DIVIDER(freq, baud, oversample) \
(((freq) + (((baud) * (oversample)) / 2U)) / ((baud) * (oversample)))

#define IFX_UART_MEM_WIDTH(cfg) \
(((cfg).dataWidth <= CY_SCB_BYTE_WIDTH) ? (CY_SCB_CTRL_MEM_WIDTH_BYTE) \
: (CY_SCB_CTRL_MEM_WIDTH_HALFWORD))
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If these are being pulled out of the code, I think it would be better to turn them into inline functions instead of macros. I find inline functions to be more readable and more maintainable.

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Updated the code to replace the macros with static inline functions as recommended.

@Deepika-aerlync Deepika-aerlync force-pushed the cy8cproto_041tp_introduction branch from 4cd4833 to a84336e Compare November 24, 2025 12:50
@zephyrbot zephyrbot added area: LVGL Light and Versatile Graphics Library Support platform: NXP NXP labels Nov 24, 2025
@Deepika-aerlync Deepika-aerlync force-pushed the cy8cproto_041tp_introduction branch from a84336e to 3fd22d4 Compare November 25, 2025 05:50
Update hal_infineon revision to add PSOC4 family support

Signed-off-by: Dharun krithik k <[email protected]>
Signed-off-by: Sayooj K Karun <[email protected]>
Signed-off-by: Deepika aerlync <[email protected]>
Add Kconfig configuration support for PSoC4 family in hal_infineon module.

Signed-off-by: Manojkumar Konisetty <[email protected]>
Signed-off-by: Sayooj K Karun <[email protected]>
Signed-off-by: Deepika aerlync <[email protected]>
Add CMake build configuration support for PSoC4 PDL and templates.

Signed-off-by: Manojkumar Konisetty <[email protected]>
Signed-off-by: Sayooj K Karun <[email protected]>
Signed-off-by: Deepika aerlync <[email protected]>
@manoj-aerlync manoj-aerlync force-pushed the cy8cproto_041tp_introduction branch from 3fd22d4 to e560bfd Compare November 25, 2025 10:20
Add base devicetree support for Infineon PSoC4100TP series including:
- Core SoC devicetree (psoc4100tp.dtsi)
- CM0+ core configuration (psoc4100tp.cm0p.dtsi)
- Pin package variants (44-TQFP, 48-QFN, 48-TQFP, 64-TQFP)
- System clocks configuration (system_clocks.dtsi)

Signed-off-by: Manojkumar Konisetty <[email protected]>
Signed-off-by: Sayooj K Karun <[email protected]>
Signed-off-by: Deepika aerlync <[email protected]>
Add devicetree support for CY8C4146 MPN variants including:
- AXI packages (T403, T413, T453)
- AZI packages (T403-T455)
- AZQ packages (T413, T453)
- LQI packages (T403, T413, T453)

Signed-off-by: Manojkumar Konisetty <[email protected]>
Signed-off-by: Sayooj K Karun <[email protected]>
Signed-off-by: Deepika aerlync <[email protected]>
Add devicetree support for CY8C4147 MPN variants including:
- AXI packages (T403-T493)
- AZI packages (T403-T475)
- AZQ packages (T415-T495)
- LQI packages (T403-T473)
- LQQ package (T493)

Signed-off-by: Manojkumar Konisetty <[email protected]>
Signed-off-by: Sayooj K Karun <[email protected]>
Signed-off-by: Deepika aerlync <[email protected]>
Add SoC port for the Infineon PSoC4100TP series, including:
- Core initialization
- Kconfig files
- YAML device definitions
- SoC-specific pin control configuration

Signed-off-by: Manojkumar Konisetty <[email protected]>
Signed-off-by: Sayooj K Karun <[email protected]>
Signed-off-by: Deepika aerlync <[email protected]>
Add board porting for the Infineon CY8CPROTO-041TP evaluation kit:
- Board devicetree and pinctrl configuration
- Kconfig and YAML definitions
- Documentation
- Support for west build, west flash, and west debug (OpenOCD)

Signed-off-by: Manojkumar Konisetty <[email protected]>
Signed-off-by: Sayooj K Karun <[email protected]>
Signed-off-by: Deepika aerlync <[email protected]>
Add clock control driver support for Infineon PSoC4:
- Fixed clock driver (clock_control_ifx_fixed_clock.c)
- Fixed factor clock driver (clock_control_ifx_fixed_factor_clock.c)
- Peripheral clock driver (clock_control_ifx_peri_clock.c)
- CAT1 clock control header

Provides clock initialization and management based on
devicetree configuration.

Signed-off-by: Dharun krithik k <[email protected]>
Signed-off-by: Sayooj K Karun <[email protected]>
Signed-off-by: Manojkumar Konisetty <[email protected]>
Signed-off-by: Deepika aerlync <[email protected]>
Add initial implementation of the Infineon PSOC4 UART driver based on the
Peripheral Driver Library (PDL) for PSOC4 (PSoC 4100TP) devices.

Features:
- UART transmit and receive using PDL SCB UART APIs
- Configurable baud rate, parity, stop bits, and data bits from devicetree
- Pinctrl integration for TX/RX pins
- Support for Zephyr console and shell subsystems
- Build-time validation for UART configuration parameters

Signed-off-by: Dharun krithik k <[email protected]>
Signed-off-by: Sayooj K Karun <[email protected]>
Signed-off-by: Manojkumar Konisetty <[email protected]>
Signed-off-by: Deepika aerlync <[email protected]>
@Deepika-aerlync Deepika-aerlync force-pushed the cy8cproto_041tp_introduction branch from e560bfd to 124a2f5 Compare November 25, 2025 17:02
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Labels

area: Boards/SoCs area: Clock Control area: Counter area: Devicetree Bindings area: I2C area: LVGL Light and Versatile Graphics Library Support area: Pinctrl area: SPI SPI bus area: UART Universal Asynchronous Receiver-Transmitter DNM (manifest) This PR should not be merged (controlled by action-manifest) manifest manifest-hal_infineon platform: Infineon Infineon Technologies AG platform: NXP NXP

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