Search results

[RISCV] Inefficient constant pool access

backend:RISC-V

Status: Open.

#153402 In llvm/llvm-project;

· asb opened on Aug 13, 2025

1 comment

[RISCV] Indent body of let scopes in RISCVInstrInfoP.td. NFC

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 153349

#153349 In llvm/llvm-project;

· topperc opened on Aug 13, 2025

· Approved

· 7/9

1

[IA][RISCV] Recognizing gap masks assembled from bitwise AND

backend:RISC-V

llvm:codegen

Status: Open (in progress).

llvm/llvm-projectnumber 153324

#153324 In llvm/llvm-project;

· mshockwave opened on Aug 13, 2025

· 7/10

3

[RISCV][VLOPT] Added support for the zvbc and the remaining zvbb instructions

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 153234

#153234 In llvm/llvm-project;

· mikhailramalho opened on Aug 12, 2025

· Approved

· 3/7

5

[libc][math][c++23] Add bf16fma{,f,l,f128} math functions

backend:AMDGPU

backend:RISC-V

libc

Status: Open (in progress).

llvm/llvm-projectnumber 153231

#153231 In llvm/llvm-project;

· krishna2803 opened on Aug 12, 2025

· 19/21

2

[RISCV] Optimize the spill/reload of segment registers

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 153184

#153184 In llvm/llvm-project;

· wangpc-pp opened on Aug 12, 2025

· 5/7

17

[Clang] Rename HasLegalHalfType -> HasFastHalfType (NFC)

backend:AArch64

backend:AMDGPU

backend:ARM

backend:DirectX

backend:Hexagon

backend:RISC-V

backend:SystemZ

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:codegenIR generation bugs: mangling, exceptions, etc.IR generation bugs: mangling, exceptions, etc.

clang:frontendLanguage frontend issues, e.g. anything involving "Sema"Language frontend issues, e.g. anything involving "Sema"

Status: Open (in progress).

llvm/llvm-projectnumber 153163

#153163 In llvm/llvm-project;

· nikic opened on Aug 12, 2025

· Approved

· 18/24

6

release/21.x: [RISCV] Cost casts with illegal types that can't be legalized (#153030)

backend:RISC-V

llvm:analysisIncludes value tracking, cost tables and constant foldingIncludes value tracking, cost tables and constant folding

Status: Open (in progress).

llvm/llvm-projectnumber 153118

#153118 In llvm/llvm-project;

· llvmbot opened on Aug 12, 2025

· 

LLVM 21.x Release

· 13/14

2

[SLPVectorizer] Widen strided loads.

backend:RISC-V

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 153074

#153074 In llvm/llvm-project;

· mgudim opened on Aug 11, 2025

· 3/7

50

[CodeGen][RISCV] Add support of RISCV nontemporal to vector predication instructions.

backend:RISC-V

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 153033

#153033 In llvm/llvm-project;

· daniel-trujillo-bsc opened on Aug 11, 2025

· 2/3

13

[TTI] Remove hasActiveVectorLength hook. NFC

backend:RISC-V

llvm:analysisIncludes value tracking, cost tables and constant foldingIncludes value tracking, cost tables and constant folding

llvm:ir

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 152977

#152977 In llvm/llvm-project;

· lukel97 opened on Aug 11, 2025

· 12/14

5

ext_vector_type crashes on bool

backend:RISC-V

clang:codegenIR generation bugs: mangling, exceptions, etc.IR generation bugs: mangling, exceptions, etc.

crashPrefer [crash-on-valid] or [crash-on-invalid]Prefer [crash-on-valid] or [crash-on-invalid]

inline-asm

Status: Open.

Bug

#152954 In llvm/llvm-project;

· 4vtomat opened on Aug 11, 2025

3 comments

[SLP]Improved/fixed FMAD support in reductions

backend:RISC-V

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 152787

#152787 In llvm/llvm-project;

· alexey-bataev opened on Aug 8, 2025

· 5/7

3

[RISCV] Update SpacemiT-X60 vector permutation instructions latencies

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 152738

#152738 In llvm/llvm-project;

· mikhailramalho opened on Aug 8, 2025

· 7/9

1

[RISCV] Update SpacemiT-X60 vector reduction operations latencies

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 152737

#152737 In llvm/llvm-project;

· mikhailramalho opened on Aug 8, 2025

· 7/9

1

[SelectionDAG] Add f16 soft promotion for lrint and lround

backend:AArch64

backend:ARM

backend:loongarch

backend:MIPS

backend:MSP430

backend:PowerPC

backend:RISC-V

backend:WebAssembly

backend:X86

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 152684

#152684 In llvm/llvm-project;

· tgross35 opened on Aug 8, 2025

· 5/7

10

Added ROLW/RORW/SLLW/SRAW/SRLW for canCreateUndefOrPoisonForTargetNode

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 152609

#152609 In llvm/llvm-project;

· badumbatish opened on Aug 7, 2025

· 5/9

2

[RISCV] Update X60 ReleaseAtCycles for Vector Integer Arithmetic Instructions

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 152557

#152557 In llvm/llvm-project;

· mikhailramalho opened on Aug 7, 2025

· 7/9

1

[VPlan] EVL transform VPVectorEndPointerRecipe alongisde load/store recipes. NFC

backend:RISC-V

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 152542

#152542 In llvm/llvm-project;

· lukel97 opened on Aug 7, 2025

· 5/7

2

Split VPlanTransforms::addExplicitVectorLength into variable step transformation and header mask optimisation

backend:RISC-V

vectorizers

Status: Open.

#152541 In llvm/llvm-project;

· lukel97 opened on Aug 7, 2025

3 comments



[RISCV]Asm Parser report error when parsing option arch directives.

backend:RISC-V

Status: Open.

#152449 In llvm/llvm-project;

· zzzhhhl opened on Aug 7, 2025

3 comments

[RISCV] Add CodeGen support for qc.insbi and qc.insb insert instructions

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 152447

#152447 In llvm/llvm-project;

· hchandel opened on Aug 7, 2025

· Approved

· 5/7

13

[LV] Add initial legality checks for loops with unbound loads.

backend:RISC-V

llvm:analysisIncludes value tracking, cost tables and constant foldingIncludes value tracking, cost tables and constant folding

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 152422

#152422 In llvm/llvm-project;

· arcbbb opened on Aug 7, 2025

· 5/7

15

Clang AST updates for more details

backend:RISC-V

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:bytecodeIssues for the clang bytecode constexpr interpreterIssues for the clang bytecode constexpr interpreter

clang:frontendLanguage frontend issues, e.g. anything involving "Sema"Language frontend issues, e.g. anything involving "Sema"

clang:openmpOpenMP related changes to ClangOpenMP related changes to Clang

HLSLHLSL Language SupportHLSL Language Support

Status: Open (in progress).

llvm/llvm-projectnumber 152372

#152372 In llvm/llvm-project;

· sei-nreimer opened on Aug 6, 2025

· Changes requested

· 9/9

8

RISC-V: How is a constant’s data type determined when it takes part in an operation.

backend:RISC-V

questionA question, not bug report. Check out https://llvm.org/docs/GettingInvolved.html instead!A question, not bug report. Check out https://llvm.org/docs/GettingInvolved.html instead!

Status: Open.

#152281 In llvm/llvm-project;

· dongyasun opened on Aug 6, 2025

3 comments