[TableGen] Emit OpName as an enum class instead of a namespace #125313
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@llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-backend-amdgpu Author: Rahul Joshi (jurahul) Changes
Patch is 50.15 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/125313.diff 24 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index ed922245b3e2ba0..198741310a0f435 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1777,7 +1777,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateMIMGDim(const MCInst &Inst, const OperandVector &Operands);
bool validateMIMGMSAA(const MCInst &Inst);
bool validateOpSel(const MCInst &Inst);
- bool validateNeg(const MCInst &Inst, int OpName);
+ bool validateNeg(const MCInst &Inst, AMDGPU::OpName OpName);
bool validateDPP(const MCInst &Inst, const OperandVector &Operands);
bool validateVccOperand(MCRegister Reg) const;
bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);
@@ -3953,8 +3953,9 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
- int RSrcOpName = (Desc.TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc
- : AMDGPU::OpName::rsrc;
+ AMDGPU::OpName RSrcOpName = (Desc.TSFlags & SIInstrFlags::MIMG)
+ ? AMDGPU::OpName::srsrc
+ : AMDGPU::OpName::rsrc;
int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, RSrcOpName);
int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);
int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16);
@@ -4651,7 +4652,7 @@ bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {
return true;
}
-bool AMDGPUAsmParser::validateNeg(const MCInst &Inst, int OpName) {
+bool AMDGPUAsmParser::validateNeg(const MCInst &Inst, AMDGPU::OpName OpName) {
assert(OpName == AMDGPU::OpName::neg_lo || OpName == AMDGPU::OpName::neg_hi);
const unsigned Opc = Inst.getOpcode();
@@ -4676,9 +4677,9 @@ bool AMDGPUAsmParser::validateNeg(const MCInst &Inst, int OpName) {
// It is convenient that such instructions don't have src_modifiers operand
// for src operands that don't allow neg because they also don't allow opsel.
- int SrcMods[3] = {AMDGPU::OpName::src0_modifiers,
- AMDGPU::OpName::src1_modifiers,
- AMDGPU::OpName::src2_modifiers};
+ const AMDGPU::OpName SrcMods[3] = {AMDGPU::OpName::src0_modifiers,
+ AMDGPU::OpName::src1_modifiers,
+ AMDGPU::OpName::src2_modifiers};
for (unsigned i = 0; i < 3; ++i) {
if (!AMDGPU::hasNamedOperand(Opc, SrcMods[i])) {
@@ -4805,9 +4806,9 @@ bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst,
}
// Returns -1 if not a register, 0 if VGPR and 1 if AGPR.
-static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx,
+static int IsAGPROperand(const MCInst &Inst, AMDGPU::OpName Name,
const MCRegisterInfo *MRI) {
- int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx);
+ int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name);
if (OpIdx < 0)
return -1;
@@ -4828,12 +4829,13 @@ bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {
SIInstrFlags::DS)) == 0)
return true;
- uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
- : AMDGPU::OpName::vdata;
+ AMDGPU::OpName DataName = (TSFlags & SIInstrFlags::DS)
+ ? AMDGPU::OpName::data0
+ : AMDGPU::OpName::vdata;
const MCRegisterInfo *MRI = getMRI();
int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MRI);
- int DataAreg = IsAGPROperand(Inst, DataNameIdx, MRI);
+ int DataAreg = IsAGPROperand(Inst, DataName, MRI);
if ((TSFlags & SIInstrFlags::DS) && DataAreg >= 0) {
int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MRI);
@@ -8647,9 +8649,8 @@ static void cvtVOP3DstOpSelOnly(MCInst &Inst, const MCRegisterInfo &MRI) {
return;
int SrcNum;
- const int Ops[] = { AMDGPU::OpName::src0,
- AMDGPU::OpName::src1,
- AMDGPU::OpName::src2 };
+ const AMDGPU::OpName Ops[] = {AMDGPU::OpName::src0, AMDGPU::OpName::src1,
+ AMDGPU::OpName::src2};
for (SrcNum = 0; SrcNum < 3 && AMDGPU::hasNamedOperand(Opc, Ops[SrcNum]);
++SrcNum)
;
@@ -8771,12 +8772,11 @@ void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)
if (OpSelIdx == -1)
return;
- const int Ops[] = { AMDGPU::OpName::src0,
- AMDGPU::OpName::src1,
- AMDGPU::OpName::src2 };
- const int ModOps[] = { AMDGPU::OpName::src0_modifiers,
- AMDGPU::OpName::src1_modifiers,
- AMDGPU::OpName::src2_modifiers };
+ const AMDGPU::OpName Ops[] = {AMDGPU::OpName::src0, AMDGPU::OpName::src1,
+ AMDGPU::OpName::src2};
+ const AMDGPU::OpName ModOps[] = {AMDGPU::OpName::src0_modifiers,
+ AMDGPU::OpName::src1_modifiers,
+ AMDGPU::OpName::src2_modifiers};
unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
@@ -8912,12 +8912,11 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
if (NegHiIdx != -1)
addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);
- const int Ops[] = { AMDGPU::OpName::src0,
- AMDGPU::OpName::src1,
- AMDGPU::OpName::src2 };
- const int ModOps[] = { AMDGPU::OpName::src0_modifiers,
- AMDGPU::OpName::src1_modifiers,
- AMDGPU::OpName::src2_modifiers };
+ const AMDGPU::OpName Ops[] = {AMDGPU::OpName::src0, AMDGPU::OpName::src1,
+ AMDGPU::OpName::src2};
+ const AMDGPU::OpName ModOps[] = {AMDGPU::OpName::src0_modifiers,
+ AMDGPU::OpName::src1_modifiers,
+ AMDGPU::OpName::src2_modifiers};
unsigned OpSel = 0;
unsigned OpSelHi = 0;
@@ -8980,7 +8979,8 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
}
static void addSrcModifiersAndSrc(MCInst &Inst, const OperandVector &Operands,
- unsigned i, unsigned Opc, unsigned OpName) {
+ unsigned i, unsigned Opc,
+ AMDGPU::OpName OpName) {
if (AMDGPU::getNamedOperandIdx(Opc, OpName) != -1)
((AMDGPUOperand &)*Operands[i]).addRegOrImmWithFPInputModsOperands(Inst, 2);
else
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 58cdbe6cf373ede..5d45c046af0fb26 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -75,8 +75,8 @@ addOperand(MCInst &Inst, const MCOperand& Opnd) {
}
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
- uint16_t NameIdx) {
- int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
+ AMDGPU::OpName Name) {
+ int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), Name);
if (OpIdx != -1) {
auto *I = MI.begin();
std::advance(I, OpIdx);
@@ -423,10 +423,11 @@ static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,
// are also tied.
unsigned Opc = Inst.getOpcode();
uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags;
- uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
- : AMDGPU::OpName::vdata;
+ AMDGPU::OpName DataName = (TSFlags & SIInstrFlags::DS)
+ ? AMDGPU::OpName::data0
+ : AMDGPU::OpName::vdata;
const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo();
- int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx);
+ int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataName);
if ((int)Inst.getNumOperands() == DataIdx) {
int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
if (IsAGPROperand(Inst, DstIdx, MRI))
@@ -922,9 +923,9 @@ static VOPModifiers collectVOPModifiers(const MCInst &MI,
bool IsVOP3P = false) {
VOPModifiers Modifiers;
unsigned Opc = MI.getOpcode();
- const int ModOps[] = {AMDGPU::OpName::src0_modifiers,
- AMDGPU::OpName::src1_modifiers,
- AMDGPU::OpName::src2_modifiers};
+ const AMDGPU::OpName ModOps[] = {AMDGPU::OpName::src0_modifiers,
+ AMDGPU::OpName::src1_modifiers,
+ AMDGPU::OpName::src2_modifiers};
for (int J = 0; J < 3; ++J) {
int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
if (OpIdx == -1)
@@ -951,15 +952,15 @@ void AMDGPUDisassembler::convertTrue16OpSel(MCInst &MI) const {
const unsigned Opc = MI.getOpcode();
const MCRegisterClass &ConversionRC =
MRI.getRegClass(AMDGPU::VGPR_16RegClassID);
- constexpr std::array<std::tuple<int, int, unsigned>, 4> OpAndOpMods = {
- {{AMDGPU::OpName::src0, AMDGPU::OpName::src0_modifiers,
- SISrcMods::OP_SEL_0},
- {AMDGPU::OpName::src1, AMDGPU::OpName::src1_modifiers,
- SISrcMods::OP_SEL_0},
- {AMDGPU::OpName::src2, AMDGPU::OpName::src2_modifiers,
- SISrcMods::OP_SEL_0},
- {AMDGPU::OpName::vdst, AMDGPU::OpName::src0_modifiers,
- SISrcMods::DST_OP_SEL}}};
+ constexpr std::array<std::tuple<AMDGPU::OpName, AMDGPU::OpName, unsigned>, 4>
+ OpAndOpMods = {{{AMDGPU::OpName::src0, AMDGPU::OpName::src0_modifiers,
+ SISrcMods::OP_SEL_0},
+ {AMDGPU::OpName::src1, AMDGPU::OpName::src1_modifiers,
+ SISrcMods::OP_SEL_0},
+ {AMDGPU::OpName::src2, AMDGPU::OpName::src2_modifiers,
+ SISrcMods::OP_SEL_0},
+ {AMDGPU::OpName::vdst, AMDGPU::OpName::src0_modifiers,
+ SISrcMods::DST_OP_SEL}}};
for (const auto &[OpName, OpModsName, OpSelMask] : OpAndOpMods) {
int OpIdx = AMDGPU::getNamedOperandIdx(Opc, OpName);
int OpModsIdx = AMDGPU::getNamedOperandIdx(Opc, OpModsName);
@@ -1069,8 +1070,9 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
AMDGPU::OpName::vdata);
int VAddr0Idx =
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
- int RsrcOpName = (TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc
- : AMDGPU::OpName::rsrc;
+ AMDGPU::OpName RsrcOpName = (TSFlags & SIInstrFlags::MIMG)
+ ? AMDGPU::OpName::srsrc
+ : AMDGPU::OpName::rsrc;
int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName);
int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
AMDGPU::OpName::dmask);
diff --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
index cc802b5fbb67c15..b22babb4a00d8f0 100644
--- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
@@ -70,9 +70,7 @@ class GCNDPPCombine {
RegSubRegPair CombOldVGPR, bool CombBCZ,
bool IsShrinkable) const;
- bool hasNoImmOrEqual(MachineInstr &MI,
- unsigned OpndName,
- int64_t Value,
+ bool hasNoImmOrEqual(MachineInstr &MI, AMDGPU::OpName OpndName, int64_t Value,
int64_t Mask = -1) const;
bool combineDPPMov(MachineInstr &MI) const;
@@ -513,7 +511,7 @@ MachineInstr *GCNDPPCombine::createDPPInst(
// returns true if MI doesn't have OpndName immediate operand or the
// operand has Value
-bool GCNDPPCombine::hasNoImmOrEqual(MachineInstr &MI, unsigned OpndName,
+bool GCNDPPCombine::hasNoImmOrEqual(MachineInstr &MI, AMDGPU::OpName OpndName,
int64_t Value, int64_t Mask) const {
auto *Imm = TII->getNamedOperand(MI, OpndName);
if (!Imm)
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index a21702af11a9840..e0850d1033e111e 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1310,7 +1310,7 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
if (!SIInstrInfo::isVALU(*MI))
return false;
- unsigned SDSTName;
+ AMDGPU::OpName SDSTName;
switch (MI->getOpcode()) {
case AMDGPU::V_READLANE_B32:
case AMDGPU::V_READFIRSTLANE_B32:
diff --git a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
index ed9c48ff9c4de4a..d0043bcc920b68e 100644
--- a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
+++ b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
@@ -308,7 +308,7 @@ bool AMDGPUCustomBehaviour::isVMEM(const MCInstrDesc &MCID) {
// taken from SIInstrInfo::hasModifiersSet()
bool AMDGPUCustomBehaviour::hasModifiersSet(
- const std::unique_ptr<Instruction> &Inst, unsigned OpName) const {
+ const std::unique_ptr<Instruction> &Inst, AMDGPU::OpName OpName) const {
int Idx = AMDGPU::getNamedOperandIdx(Inst->getOpcode(), OpName);
if (Idx == -1)
return false;
diff --git a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
index 3a231758887ba60..85b9c188b5d1a77 100644
--- a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
+++ b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
@@ -17,6 +17,7 @@
#ifndef LLVM_LIB_TARGET_AMDGPU_MCA_AMDGPUCUSTOMBEHAVIOUR_H
#define LLVM_LIB_TARGET_AMDGPU_MCA_AMDGPUCUSTOMBEHAVIOUR_H
+#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/MCA/CustomBehaviour.h"
#include "llvm/TargetParser/TargetParser.h"
@@ -66,7 +67,7 @@ class AMDGPUCustomBehaviour : public CustomBehaviour {
void generateWaitCntInfo();
/// Helper function used in generateWaitCntInfo()
bool hasModifiersSet(const std::unique_ptr<Instruction> &Inst,
- unsigned OpName) const;
+ AMDGPU::OpName OpName) const;
/// Helper function used in generateWaitCntInfo()
bool isGWS(uint16_t Opcode) const;
/// Helper function used in generateWaitCntInfo()
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index c389f3a13d95241..381841f1428553e 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -1205,7 +1205,7 @@ void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
int NumOps = 0;
int Ops[3];
- std::pair<int, int> MOps[] = {
+ std::pair<AMDGPU::OpName, AMDGPU::OpName> MOps[] = {
{AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src0},
{AMDGPU::OpName::src1_modifiers, AMDGPU::OpName::src1},
{AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::src2}};
@@ -1226,7 +1226,7 @@ void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsWMMA) {
NumOps = 0;
int DefaultValue = Mod == SISrcMods::OP_SEL_1;
- for (int OpName :
+ for (AMDGPU::OpName OpName :
{AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
AMDGPU::OpName::src2_modifiers}) {
int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index b9a424bb1d05903..1391ef6dd09e54a 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -340,14 +340,13 @@ AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO,
uint64_t AMDGPUMCCodeEmitter::getImplicitOpSelHiEncoding(int Opcode) const {
using namespace AMDGPU::VOP3PEncoding;
- using namespace AMDGPU::OpName;
- if (AMDGPU::hasNamedOperand(Opcode, op_sel_hi)) {
- if (AMDGPU::hasNamedOperand(Opcode, src2))
+ if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::op_sel_hi)) {
+ if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2))
return 0;
- if (AMDGPU::hasNamedOperand(Opcode, src1))
+ if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src1))
return OP_SEL_HI_2;
- if (AMDGPU::hasNamedOperand(Opcode, src0))
+ if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src0))
return OP_SEL_HI_1 | OP_SEL_HI_2;
}
return OP_SEL_HI_0 | OP_SEL_HI_1 | OP_SEL_HI_2;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
index 879dbe1b279b184..9c0b2da0fcb0a2d 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
@@ -50,7 +50,6 @@ createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
#include "AMDGPUGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
-#define GET_INSTRINFO_OPERAND_ENUM
#define GET_INSTRINFO_MC_HELPER_DECLS
#include "AMDGPUGenInstrInfo.inc"
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCTargetDesc.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCTargetDesc.h
index cf40e7eccb5d246..20f2cb826ac4b1b 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCTargetDesc.h
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCTargetDesc.h
@@ -32,7 +32,6 @@ MCInstrInfo *createR600MCInstrInfo();
#include "R600GenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
-#define GET_INSTRINFO_OPERAND_ENUM
#define GET_INSTRINFO_SCHED_ENUM
#define GET_INSTRINFO_MC_HELPER_DECLS
#include "R600GenInstrInfo.inc"
diff --git a/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp b/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
index ef2d049f9175264..429ce0e0857acba 100644
--- a/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
@@ -31,7 +31,7 @@ class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
const R600InstrInfo *TII = nullptr;
void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI,
- unsigned Op);
+ R600::OpName Op);
public:
static char ID;
@@ -61,7 +61,8 @@ FunctionPass *llvm::createR600ExpandSpecialInstrsPass() {
}
void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,
- const MachineInstr *OldMI, unsigned Op) {
+ const MachineInstr *OldMI,
+ R600::OpName Op) {
int OpIdx = TII->getOperandIdx(*OldMI, Op);
if (OpIdx > -1) {
uint64_t Val = OldMI->getOperand(OpIdx).getImm();
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index f95649db2942ec9..1c4a992c8727162 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -222,19 +222,18 @@ bool R600InstrInfo::readsLDSSrcReg(const MachineInstr &MI) const {
}
int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
- static const unsigned SrcSelTable[][2] = {
- {R600::OpName::src0, R600::OpName::src0_sel},
- {R600::OpName::src1, R600::OpName::src1_sel},
- {R600::OpName::src2, R600::OpName::src2_sel},
- {R600::OpName::src0_X, R600::OpName::src0_sel_X},
- {R600::OpName::src0_Y, R600::OpName::src0_sel_Y},
- {R600::OpName::src0_Z, R600::OpName::src0_sel_Z},
- {R600::OpName::src0_W, R600::OpName::src0_sel_W},
- {R600::OpName::src1_X, R600::OpName::src1_sel_X},
- {R600::OpName::src1_Y, R600::OpName::src1_sel_Y},
- {R600::OpName::src1_Z, R600::OpName::src1_sel_Z},
- {R600::OpName::src1_W, R600::OpName::src1_sel_W}
- };
+ static const R600:...
[truncated]
|
|
I wanted to see if this change makes sense and any issues it could potentially have for downstream components. There is a lot of mostly mechanical churn. |
I don't think it needs to be deprecated, this is a trivial change. |
Done. |
|
The |
Right. I had that at the back of my mind, I started this as a prototype and then forgot to do it. Updated the documentation as well. |
Also, this might be obvious, but if/when this lands, please cherry-pick into the NV-internal trybot since it won't merge cleanly. I'll do the same in a second backend I'm responsible for. |
Yeah, I have them in an internal branch as well, ready to merge when this change (if committed) lands internally. |
mshockwave
reviewed
Feb 3, 2025
Sure will do. |
|
All checks are clean now. Starting review. |
topperc
reviewed
Feb 4, 2025
|
@arsenm @jayfoad any feedback on the AMDGPU side? @topperc @s-barannikov @mshockwave would appreciate if you can PTAL as well. |
jayfoad
reviewed
Feb 5, 2025
|
Resolving conflicts with latest AMDGPU changes. |
|
@topperc, @s-barannikov, @arsenm another friendly ping. It seems AMDGPU folks are fine (@jayfoad). Once its approved, I can hold off on committing for a few days in case downstream backends that are in sync with upstream need to prepare for it (I'll be doing the same for NVIDIA internal code). May be send a PSA on discourse as well if needed. |
|
Thanks. Will commit sometime mid next week. |
- Change InstrInfoEmitter to emit OpName as an enum class instead of an anonymous enum in the OpName namespace. - This will help clearly distinguish between vales that are OpNames vs just operand indices and should help avoid bugs due to confusion between the two. - Also updated AMDGPU, RISCV, and WebAssembly backends to conform to the new definition of OpName (mostly mechanical changes).
arsenm
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Feb 12, 2025
flovent
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…125313) - Change InstrInfoEmitter to emit OpName as an enum class instead of an anonymous enum in the OpName namespace. - This will help clearly distinguish between values that are OpNames vs just operand indices and should help avoid bugs due to confusion between the two. - Rename OpName::OPERAND_LAST to NUM_OPERAND_NAMES. - Emit declaration of getOperandIdx() along with the OpName enum so it doesn't have to be repeated in various headers. - Also updated AMDGPU, RISCV, and WebAssembly backends to conform to the new definition of OpName (mostly mechanical changes).
joaosaffran
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Feb 14, 2025
…125313) - Change InstrInfoEmitter to emit OpName as an enum class instead of an anonymous enum in the OpName namespace. - This will help clearly distinguish between values that are OpNames vs just operand indices and should help avoid bugs due to confusion between the two. - Rename OpName::OPERAND_LAST to NUM_OPERAND_NAMES. - Emit declaration of getOperandIdx() along with the OpName enum so it doesn't have to be repeated in various headers. - Also updated AMDGPU, RISCV, and WebAssembly backends to conform to the new definition of OpName (mostly mechanical changes).
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instead of an anonymous enum in the OpName namespace.
OpNames vs just operand indices and should help avoid
bugs due to confusion between the two.
enum so it doesn't have to be repeated in various headers.
to conform to the new definition of OpName (mostly
mechanical changes).