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What

Nine D16 format loads were rejected by the decoder:

• MUBUF: buffer_load_format_d16_{x,xy,xyz,xyzw} (0x80-0x83) and buffer_load_format_d16_hi_x (0x26).
• MTBUF: tbuffer_load_format_d16_{x,xy,xyz,xyzw} (0x08-0x0b).

The ISA sweep only covered MUBUF opcodes below 0x80, which is why it missed the first four. They load a formatted element like the 32-bit forms, convert each component to 16 bits, and pack two per VGPR.

Semantics measured on an RDNA2 GPU (ROCm HSA, raw kernels; 3344 vectors per format, all matched by a Python model):

Component type	16-bit result
UNORM / SNORM	f16 of the exact value v/(2^n−1), round to nearest even (SNORM clamps to −1)
USCALED / SSCALED	f16 round to nearest even, overflow saturates to ±65504
32-bit FLOAT	f16 round toward zero, overflow to ±65504, inf stays inf, NaN keeps its top payload bits (at least 1)
16-bit FLOAT	passthrough
UINT / SINT	8/16-bit: low 16 bits; 32-bit: saturated to u16 / i16

Packing:

• _x writes the low half and keeps the high half. _hi_x writes the high half and keeps the low half.
• _xy and _xyzw overwrite their registers.
• _xyz keeps the upper half of its second register.
• Components the format lacks are 0. A descriptor-swizzle constant one is f16 1.0 (0x3c00) for non-integer formats and 1 for UINT/SINT.

Implementation:

• MemoryInfo::d16 marks the load.
• The backend's formatted-load path calls EmitD16FormatComponent instead of NormalizeFormatComponent. It uses integer ops only (q = (v << s) / M with the remainder for UNORM/SNORM, mantissa truncation for RTZ), so results don't depend on the driver's f32→f16 rounding.
• Going through an f32 division and then a f16 conversion would double-round 4 of the 16-bit UNORM/SNORM values (e.g. 0xffaf). The test includes them.
• Translation packs the halves. _x/_hi_x reuse the d16Half destination selector from feat(shader): implement the D16 byte/short loads and high-half stores #319.

D16 format stores are not part of this PR. The existing formatted stores don't convert to the format yet, and that will be a separate change.

Test agc_driver_format_d16: 16 results × 32 lanes captured on the RDNA2 GPU. It covers every component type above, the double-rounding cases, f32 specials (±inf, NaN payloads, 65520, overflow and subnormal edges), every packing form including the preserved halves, and a descriptor built in the shader with swizzle x,0,1,1.

Tested

Linux, full ctest (100) passes.

• RADV (Radeon 660M) and lavapipe: the test passes.
• Without the D16 conversion: 8unorm is 0xdead0000, expected 0xdead3c00. Without the f16 one constant: xyzw_hi is 0x3f800000, expected 0x3c003c00.

Checklist

• Based on current main; no other open PR implements the same functions
• One topic per PR; follow-ups go in a new PR
• No comments in code except technical debt
• Unimplemented paths throw (NotImplemented_nid_no_patch); silent stubs are listed in TechnicalDebt
• No notes, investigation .md files or images added to the repository (attach them to this PR)
• New third-party code is a submodule built from source
• Generic behaviour, not specific to one title
• Depends on: ci: run the shader execution tests on lavapipe #251 (test harness), feat(shader): implement the D16 byte/short loads and high-half stores #319 (D16 loads, d16Half); review only the last commit
• AI-assisted: yes

[github-actions]

Progress report (d3ec1f1 → 5c8c5d2)

📈 GPU shader instructions: 74.96% (+3.95%, +46 implemented instructions)

✅ 46 implemented

Encoding	Name
DS	DS_READ_I8_D16
DS	DS_READ_I8_D16_HI
DS	DS_READ_U8_D16
DS	DS_READ_U8_D16_HI
DS	DS_WRITE_B8_D16_HI
FLAT	FLAT_LOAD_SBYTE_D16
FLAT	FLAT_LOAD_SBYTE_D16_HI
FLAT	FLAT_LOAD_SHORT_D16
FLAT	FLAT_LOAD_SHORT_D16_HI
FLAT	FLAT_LOAD_UBYTE_D16
FLAT	FLAT_LOAD_UBYTE_D16_HI
FLAT	FLAT_STORE_BYTE_D16_HI
FLAT	FLAT_STORE_SHORT_D16_HI
GLOBAL	GLOBAL_LOAD_SBYTE_D16
GLOBAL	GLOBAL_LOAD_SBYTE_D16_HI
GLOBAL	GLOBAL_LOAD_SHORT_D16
GLOBAL	GLOBAL_LOAD_SHORT_D16_HI
GLOBAL	GLOBAL_LOAD_UBYTE_D16
GLOBAL	GLOBAL_LOAD_UBYTE_D16_HI
GLOBAL	GLOBAL_STORE_BYTE_D16_HI
GLOBAL	GLOBAL_STORE_SHORT_D16_HI
MTBUF	TBUFFER_LOAD_FORMAT_D16_X
MTBUF	TBUFFER_LOAD_FORMAT_D16_XY
MTBUF	TBUFFER_LOAD_FORMAT_D16_XYZ
MTBUF	TBUFFER_LOAD_FORMAT_D16_XYZW
MUBUF	BUFFER_LOAD_FORMAT_D16_HI_X
MUBUF	BUFFER_LOAD_FORMAT_D16_X
MUBUF	BUFFER_LOAD_FORMAT_D16_XY
MUBUF	BUFFER_LOAD_FORMAT_D16_XYZ
MUBUF	BUFFER_LOAD_FORMAT_D16_XYZW
MUBUF	BUFFER_LOAD_SBYTE_D16
MUBUF	BUFFER_LOAD_SBYTE_D16_HI
MUBUF	BUFFER_LOAD_SHORT_D16
MUBUF	BUFFER_LOAD_SHORT_D16_HI
MUBUF	BUFFER_LOAD_UBYTE_D16
MUBUF	BUFFER_LOAD_UBYTE_D16_HI
MUBUF	BUFFER_STORE_BYTE_D16_HI
MUBUF	BUFFER_STORE_SHORT_D16_HI
SCRATCH	SCRATCH_LOAD_SBYTE_D16
SCRATCH	SCRATCH_LOAD_SBYTE_D16_HI
SCRATCH	SCRATCH_LOAD_SHORT_D16
SCRATCH	SCRATCH_LOAD_SHORT_D16_HI
SCRATCH	SCRATCH_LOAD_UBYTE_D16
SCRATCH	SCRATCH_LOAD_UBYTE_D16_HI
SCRATCH	SCRATCH_STORE_BYTE_D16_HI
SCRATCH	SCRATCH_STORE_SHORT_D16_HI