[oneandonlydean]

What

Follow-up to #254, as discussed there: #254 masks the v_writelane_b32 lane select, and adriadam10 left v_readlane_b32 / Shuffle for this PR ("I left v_readlane_b32 / Shuffle for your follow-up, as you offered.").

The hardware reads the v_readlane_b32 lane select modulo the wave size: S1[4:0] in wave32, S1[5:0] in wave64. ReadLaneEliminator already assumes this for constant lanes (selector % waveSize), and the two-lane wave64 path in SpirvValueEmitContext::Shuffle already wraps (it masks with 31 and picks the half from bit 5). The single-subgroup path did not: EmitReadLane passed the raw select straight to OpGroupNonUniformShuffle, which is undefined for an id at or above the subgroup size. A wave32 v_readlane_b32 s8, v4, 37 emitted OpGroupNonUniformShuffle %uint %uint_3 %v4 %uint_37.

Changes:

• EmitReadLane masks the lane select with WaveSize() - 1 before Shuffle, the same expression EmitWriteLane uses after fix(shader): select the written lane in v_writelane_b32 #254. On the two-lane path the extra AND is redundant and folds away.
• The constant-lane fold in ReadLaneEliminator does not cover this: it only rewrites a read it can resolve to a v_writelane chain or a unique lane value, so other constant lanes (and every SGPR-selected lane) still reach the emitter.
• v_readfirstlane_b32 is not changed here. Its lane comes from OpGroupNonUniformBallotFindLSB (or FirstLane on the two-lane path), which is in range whenever a lane is active. With an empty EXEC it is undefined on the single-subgroup path and lane 31 on the two-lane path, while the hardware reads lane 0. That is a separate fix, which I'll send after this one.

Test agc_driver_read_lane, in the style of #254's agc_driver_write_lane (words from llvm-mc -mcpu=gfx1013): a 32-thread wave32 dispatch where every lane reads v_readlane_b32 with an inline lane of 37, then with an SGPR lane of 69 taken from v_readfirstlane_b32 of a loaded value. Both must return lane 5's value, and the third result checks the v_readfirstlane_b32 value. Like the write-lane test, it is skipped when the subgroup cannot hold a wave32 (lavapipe: 8).

Tested

• Linux (CachyOS, GCC), NVIDIA RTX 4090 (subgroup size 32). ctest: 100/100 pass, including the new test.
• Without the mask the test also passes on the RTX 4090. The SPIR-V shows the unmasked OpGroupNonUniformShuffle with lane 37 (and the dynamic lane 69), so NVIDIA happens to wrap the out-of-range id itself; the result is still undefined by the spec. On a device that runs a wave32 program on a 64-wide subgroup (RADV without fix(agc): run wave32 compute programs on 32-wide subgroups #316), lane 37 is an invocation outside the 32-thread dispatch, so I expect the old code to fail there, but I have no AMD GPU to check it.
• lavapipe: skipped (subgroup size 8).

Checklist

• Based on current main; no other open PR implements the same functions
• One topic per PR; follow-ups go in a new PR
• No comments in code except technical debt
• Unimplemented paths throw (NotImplemented_nid_no_patch); silent stubs are listed in TechnicalDebt
• No notes, investigation .md files or images added to the repository
• New third-party code is a submodule built from source (none added)
• Generic behaviour, not specific to one title
• Depends on: none (fix(shader): select the written lane in v_writelane_b32 #254 and ci: run the shader execution tests on lavapipe #251 have merged)
• AI-assisted: yes